參數資料
型號: V385GLFT
英文描述: 8-BIT LVDS TRANSMITTER FOR VIDEO
中文描述: 8位LVDS的視頻信號輸出
文件頁數: 1/9頁
文件大?。?/td> 158K
代理商: V385GLFT
V385
8-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V385 Datasheet
1
3/30/05
Revision 1.6
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
General Description
The V385 transmitter converts 28 bits of 3.3 V
CMOS/TTL into 4 Low Voltage Differential Signaling
(LVDS) data streams while the transmit clock input is
transmitted in parallel with the data streams over a fifth
LVDS link. The V385 can be programmed for rising
edge or falling edge clocks through pin R_FB.
ICS manufactures a large variety of video application
devices. Consult ICS for all of your video application
requirements.
Pin Assignment
Features
Pin and function compatible with the National
DS90C385, TI SN65LVDS93 and THine
THC63LVDM83
Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS
streams
Up to 2.38 Gbps throughput or 297.5 Megabytes/sec
bandwidth
Wide clock frequency range from 20 MHz to 85 MHz
Spread spectrum compatible
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Single 3.3 V low-power CMOS design
Programmable rising or falling edge strobe
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
12
13
1
2
3
4
5
6
7
8
11
10
VCC
TxIN5
TxIN6
TxIN7
GND
9
16
17
18
19
20
21
22
23
24
25
26
27
28
15
14
56-pin TSSOP
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
TxIN8
TxIN9
TxIN10
VCC
TxIN11
TxIN12
TxIN13
GND
TxIN14
TxIN15
TxIN16
R_FB
TxIN17
TxIN18
TxIN19
GND
TxIN20
TxIN21
TxIN22
TxIN23
VCC
TxIN24
TxIN25
GND
TxIN26
PWRDWN
TxCLKIN
PLL_GND
PLL_GND
PLL_VCC
LVDS_GND
LVDS_GND
TxOUT2-
LVDS_GND
TxOUT0-
LVDS_VCC
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-
TxOUT2+
TxOUT1+
TxOUT1-
TxOUT0+
TxIN27
TxIN0
TxIN1
GND
TxIN2
TxIN3
TxIN4
TTL to
LVDS
TxOUT0+
PLL
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-
24
Red, Green, Blue
CLOCK
PWRDWN
R_FB
CONTROL
DATA ENABLE
VSYNC
HSYNC
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