參數(shù)資料
型號: V436416S04V
廠商: Mosel Vitelic, Corp.
英文描述: 3.3 VOLT 16M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE
中文描述: 3.3伏16米x 64高性能PC100的無緩沖內存模塊
文件頁數(shù): 7/11頁
文件大?。?/td> 65K
代理商: V436416S04V
MOSEL VITELIC
V436416S04V(C)TG-10PC
7
V436416S04V(C)TG-10PC Rev. 1.2 June 2000
AC Characteristics
3,4
T
A
= 0
°
to 70
°
C; V
SS
= 0V; V
CC
= 3.3V
±
0.3V, t
T
= 1 ns
#
Symbol
Parameter
Limit Values
Unit
Note
-10PC
Min.
Max.
Clock and Clock Enable
1
t
CK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
10
10
ns
ns
2
f
CK
System frequency
CAS Latency = 3
CAS Latency = 2
100
100
MHz
MHz
3
t
AC
Clock Access Time
CAS Latency = 3
CAS Latency = 2
6
6
ns
ns
4,5
4
t
CH
Clock High Pulse Width
3
ns
6
5
t
CL
Clock Low Pulse Width
3
ns
6
6
t
CS
Input Setup time
2
ns
7
7
t
CH
Input Hold Time
1
ns
7
8
t
CKSP
CKE Setup Time (Power down mode)
2.5
ns
8
9
t
CKSR
CKE Setup Time (Self Refresh Exit)
8
ns
9
10
t
T
Transition time (rise and fall)
1
ns
Common Parameters
11
t
RCD
RAS to CAS delay
20
ns
12
t
RC
Cycle Time
70
120k
ns
13
t
RAS
Active Command Period
45
ns
14
t
RP
Precharge Time
20
ns
15
t
RRD
Bank to Bank Delay Time
16
ns
16
t
CCD
CAS to CAS delay time
(same bank)
1
CLK
Refresh Cycle
17
t
SREX
Self Refresh Exit Time
10
ns
9
18
t
REF
Refresh Period (4096 cycles)
64
ms
8
Read Cycle
19
t
OH
Data Out Hold Time
3
ns
4
20
t
LZ
Data Out to Low Impedance Time
0
ns
21
t
HZ
Data Out to High Impedance Time
3
9
ns
10
22
t
DQZ
DQM Data Out Disable Latency
2
CLK
Write Cycle
23
t
DPL
Data input to Precharge (write recovery)
2
CLK
24
t
DAL
Data In to Active/refresh
5
CLK
11
25
t
DQW
DQM Write Mask Latency
0
CLK
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