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參數(shù)資料
| 型號： | V43644R04VTG |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 3.3 Volt 4M x 64 High Performance PC100 and 100 MHZ SDRAM Module with Unbuffered(3.3V 4M*64位高性能無緩沖器PC100和100MHZ SDRAM模塊) |
| 中文描述： | 3.3伏特4米× 64高性能和100兆赫PC100的內(nèi)存模塊，緩沖（3.3分* 64位高性能無緩沖器PC100的SDRAM內(nèi)存和100MHZ輸出模塊） |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 64K |
| 代理商： | V43644R04VTG |
4
V43644R04VTG Rev. 1.0 February 1999
MOSEL V ITELIC
V43644R04VTG
Serial Presence Detect Information
A serial presence detect storage device -
E
PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
PD-Table:
2
written into the E
duction using a serial presence detect protocol (I
synchronous 2-wire bus)
2
PROM device during module pro-
2
C
Byte
Number
Function Described
SDP Entry Value
Hex Value
100 MHz
-10PC
100 MHz
-10
83 MHz
-12
0
Number of SPD bytes
128
80
80
80
1
Total bytes in Serial PD
256
08
08
08
2
Memory Type
SDRAM
04
04
04
3
Number of Row Addresses (without BS bits)
12
0C
0C
0C
4
Number of Column Addresses (for x16 SDRAM)
8
08
08
08
5
Number of DIMM Banks
1
01
01
01
6
Module Data Width
64
40
40
40
7
Module Data Width (continued)
0
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
9
SDRAM Cycle Time at CL=3
10.0 ns / 12.0 ns
A0
A0
C0
10
SDRAM Access Time from Clock at CL=3
6.0 ns / 7.0 ns / 8.0 ns
60
70
80
11
Dimm Config (Error Det/Corr.)
none
00
00
00
12
Refresh Rate/Type
Self-Refresh, 15.6
m
s
80
80
80
13
SDRAM width, Primary
x16
10
10
10
14
Error Checking SDRAM Data Width
n/a / x8
00
00
00
15
Minimum Clock Delay from Back to Back
Random Column Address
t
ccd
= 1 CLK
01
01
01
16
Burst Length Supported
1, 2, 4, 8 & full Page
8F
8F
8F
17
Number of SDRAM Banks
4
04
04
04
18
Supported CAS Latencies
CL = 2 & 3
06
06
06
19
CS Latencies
CS Latency = 0
01
01
01
20
WE Latencies
WL = 0
01
01
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
00
00
22
SDRAM Device Attributes: General
Vcc tol
±
10%
06
06
06
23
Minimum Clock Cycle Time at CAS Latency = 2
10.0 ns / 12.0 ns
A0
C0
C0
24
Maximum Data Access Time from Clock for CL = 2
6.0 ns / 7.0 ns / 8.0 ns
60
70
80
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
00
00
26
Maximum Data Access Time from Clock at CL = 1
Not Supported
00
00
00
27
Minimum Row Precharge Time t
RP
20 ns / 24 ns
14
18
18
28
Minimum Row Active to Row Active Delay t
RRD
16 ns / 20 ns
10
14
14
29
Minimum RAS to CAS Delay t
RCD
20 ns / 24 ns
14
18
18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V43644Y04VCTG-10PC | 3.3 VOLT 4M x 64 HIGH PERFORMANCE 100 MHZ SDRAM UNBUFFERED SODIMM |
| V43644Y04VCTG-75 | 3.3 VOLT 4M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SODIMM |
| V43644Y04VTG-10PC | 3.3 VOLT 4M x 64 HIGH PERFORMANCE 100 MHZ SDRAM UNBUFFERED SODIMM |
| V43644YO4VTG | 3.3 Volt 4M x 64 High Performance 100 MHZ SDRAM Module with Unbuffered(3.3V 4M*64位高性能無緩沖器100MHZ SDRAM模塊) |
| V43648S04VCTG-10PC | 3.3 VOLT 8M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V43644Y04VCTG-10PC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 4M x 64 HIGH PERFORMANCE 100 MHZ SDRAM UNBUFFERED SODIMM |
| V43644Y04VCTG-75 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 4M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SODIMM |
| V43644Y04VTG-10PC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 4M x 64 HIGH PERFORMANCE 100 MHZ SDRAM UNBUFFERED SODIMM |
| V43648S04VCTG-10PC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 8M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE |
| V43648S04VCTG-75 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 8M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SDRAM MODULE |
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