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參數資料
| 型號： | V43644YO4VTG |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 3.3 Volt 4M x 64 High Performance 100 MHZ SDRAM Module with Unbuffered(3.3V 4M*64位高性能無緩沖器100MHZ SDRAM模塊) |
| 中文描述： | 3.3伏特4米× 64高性能100 MHz的內存模塊，緩沖（3.3分* 64位高性能無緩沖器100MHZ輸出內存模塊） |
| 文件頁數： | 8/10頁 |
| 文件大?。?/td> | 57K |
| 代理商： | V43644YO4VTG |
8
V43644Y04VTG Rev. 1.5 February 1999
MOSEL V ITELIC
V43644Y04VTG
Notes:
1.
The specified values are valid when addresses are changed no more than once during t
CK
(min.) and when No
Operation commands are registered on every rising clock edge during t
RC
(min). Values are shown per module
bank.
2.
The specified values are valid when data inputs (DQ’s) are stable during t
RC
(min.).
3.
All AC characteristics are shown for device level.
An initial pause of 100
m
s is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4.
AC timing tests have V
IL
= 0.4V and V
IH
= 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between V
IH
and V
IL
. All AC measurements assume t
T
= 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
5.
If clock rising time is longer than 1 ns, a time (t
T
/2 -0.5) ns has to be added to this parameter.
6.
Rated at 1.5V
7.
If t
T
is longer than 1 ns, a time (t
T
-1) ns has to be added to this parameter.
8.
Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9.
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to t
RC
is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
t
DAL
is equivalent to t
DPL
+ t
RP
.
1.4V
1.4V
tSETUP
tHOLD
tAC
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
2.4V
0.4V
t
T
tCL
tCH
I/O
Measurement conditions for
tac and toh
50 pF
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相關代理商/技術參數 |
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|---|---|
| V43648S04VCTG-10PC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 8M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE |
| V43648S04VCTG-75 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 8M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SDRAM MODULE |
| V43648Y04VCTG-10PC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 8M x 64 HIGH PERFORMANCE 100 MHZ SDRAM UNBUFFERED SODIMM |
| V43648Y04VCTG-75 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 8M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SODIMM |
| V43648Z04VCTG-75 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:3.3 VOLT 8M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SODIMM |
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