參數(shù)資料
型號: V43648Z04VTG
廠商: Mosel Vitelic, Corp.
英文描述: 3.3 Volt 8M x 64 High Performance 100 MHZ SDRAM Module with Unbuffered(3.3V 8M*64位高性能無緩沖器100MHZ的SDRAM模塊)
中文描述: 3.3伏800萬× 64高性能100 MHz的內(nèi)存模塊,緩沖(3.3分* 64位高性能無緩沖器100MHZ輸出的內(nèi)存模塊)
文件頁數(shù): 5/10頁
文件大小: 60K
代理商: V43648Z04VTG
MOSEL V ITELIC
V43648Z04VTG
5
V43648Z04VTG Rev. 1.6 February 1999
Absolute Maximum Ratings
DC Characteristics
T
A
= 0
°
C to 70
°
C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
±
0.3V
30
Minimum RAS Pulse Width t
RAS
45 ns
2D
31
Module Bank Density (Per Bank)
64 MByte
10
32
SDRAM Input Setup Time
2.0 ns
20
33
SDRAM Input Hold Time
1 ns
10
34
SDRAM Data Input Setup Time
2.0 ns
20
35
SDRAM Data Input Hold Time
1 ns
10
36-61
Superset Information (May be used in Future)
00
62
SPD Revision
Revision 1
12
63
Checksum for Bytes 0 - 62
F4
64-125
Manufacturers’s Information (Optional)
(FFh if not used)
XX
126
Max. Frequency Specification
100 MHz
64
127
100 MHz Support Details
AF
128+
Unused Storage Location
00
Parameter
Max.
Units
Voltage on VDD Supply Relative to V
SS
-1 to 4.6
V
Voltage on Input Relative to V
SS
-1 to 4.6
V
Operating Temperature
0 to +70
°
C
Storage Temperature
-55 to 125
°
C
Power Dissipation
8
W
Symbol
Parameter
Limit Values
Unit
Min.
Max.
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
V
IL
Input Low Voltage
–0.5
0.8
V
V
OH
Output High Voltage (I
OUT
= –2.0 mA)
2.4
V
V
OL
Output Low Voltage (I
OUT
= 2.0 mA)
0.4
V
I
I(L)
Input Leakage Current, any input
(0 V < V
IN
< 3.6 V, all other inputs = 0V)
–40
40
m
A
I
O(L)
Output leakage current
(DQ is disabled, 0V < V
OUT
< V
CC
)
–40
40
m
A
SPD-Table for -10 PC modules: (Continued)
Byte
Number
Function Described
SDP Entry Value
Hex Value
100 MHz
-10PC
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