參數(shù)資料
型號(hào): V54C3256164VBJ7PC
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封裝: LEAD FREE, MO-210, FBGA-60
文件頁(yè)數(shù): 3/50頁(yè)
文件大?。?/td> 728K
代理商: V54C3256164VBJ7PC
11
V54C3256(16/80/40)4VB Rev. 1.0 December 2003
ProMOS TECHNOLOGIES
V54C3256(16/80/40)4VB
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Notes:
1.
V = Valid , x = Don’t Care, L = Low Level, H = High Level
2.
CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3.
These are state of bank designated by BS0, BS1 signals.
4.
Power Down Mode can not entry in the burst cycle.
Operation
Device
State
CKE
n-1
CKE
nCS
RAS
CAS
WE
DQM
A0-9,
A11,
A12
A10
BS0
BS1
Row Activate
Idle
3
HX
L
H
X
V
Read
Active
3
H
X
L
H
L
H
XVL
V
Read w/Autoprecharge
Active3
HX
L
H
L
H
X
V
H
V
Write
Active3
H
X
L
H
L
XVL
V
Write with Autoprecharge
Active3
HX
L
H
L
X
V
H
V
Row Precharge
Any
H
X
L
H
L
X
L
V
Precharge All
Any
H
X
L
H
L
X
H
X
Mode Register Set
Idle
H
X
L
X
V
No Operation
Any
H
X
L
H
X
Device Deselect
Any
H
X
H
X
Auto Refresh
Idle
H
L
H
X
Self Refresh Entry
Idle
H
L
H
X
Self Refresh Exit
Idle
(Self Refr.)
L
H
HX
X
XX
X
L
HHX
Power Down Entry
Idle
Active4
HL
HX
X
XX
X
L
HHX
Power Down Exit
Any
(Power
Down)
LH
HX
X
XX
X
LH
H
L
Data Write/Output Enable
Active
H
X
L
X
Data Write/Output Disable
Active
H
X
H
X
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