參數(shù)資料
型號(hào): V58C2256404SBJ5
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 64M X 4 DDR DRAM, 0.65 ns, PBGA60
封裝: LEAD FREE, MO-233, FBGA-60
文件頁數(shù): 9/62頁
文件大?。?/td> 983K
代理商: V58C2256404SBJ5
17
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SB
V58C2256(804/404/164)SB Rev. 1.0 November 2003
Precharge Timing During Read Operation
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read
burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time
(t
RP). A Precharge command can not be issued until tRAS(min) is satisfied.
Read with Precharge Timing as a Function of CAS Latency
T0
T1
T2
T3
T4
T5
T6
T7
T8
D0
D1
D2
D3
NOP
Read
NOP
PreA
NOP
BA
NOP
CK, CK
Command
DQS
DQ
tRAS(min)
tRP(min)
BA
NOP
T9
D0
D1
D2
D3
DQS
DQ
CAS Latency=2
CAS Latency=2.5
(CAS Latency = 2, 2.5; Burst Length = 4)
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