參數(shù)資料
型號(hào)： V59C1512804QAUF25AI
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 64M X 8 DDR DRAM, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁數(shù)： 8/79頁
文件大小： 1028K
代理商： V59C1512804QAUF25AI
16
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Off- Chip-Driver Adjust Program
4 bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
00
0
NOP (no operation)
00
0
1
Increase by 1 step
NOP
00
1
0
Decrease by 1 step
NOP
01
0
NOP
Increase by 1 step
10
0
NOP
Decrease by 1 step
01
0
1
Increase by 1 step
01
1
0
Decrease by 1 step
Increase by 1 step
10
0
1
Increase by 1 step
Decrease by 1 step
10
1
0
Decrease by 1 step
Other Combinations
Reserved
For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the fol-
lowing timing diagram. Input data pattern for adjustment, DT0 - DT3 is fixed and not affected by MRS
addressing mode (i.e. sequential or interleave). Burst length of 4 have to be programmed in the MRS for OCD
impedance adjustment.
NOP
EMRS
CMD
CK
DQS_in
DQ_in
tDS tDH
WL
OCD adj ust mode
OCD calibratio n mode exit
tWR
EMRS
CK
DQS
NOP
DT0
DT1
DT2
DT3
相關(guān)PDF資料
PDF描述
V59C1512808QALF37E 64M X 8 DDR DRAM, BGA68
V59C1512808QALJ3H 64M X 8 DDR DRAM, PBGA68
V59C1512808QAUF19 64M X 8 DDR DRAM, PBGA68
V59C1512808QAUF5H 64M X 8 DDR DRAM, PBGA68
V59C1512804QALJ-37 64M X 8 DDR DRAM, 0.5 ns, PBGA68
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