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參數(shù)資料
| 型號： | V59C1G01808QAUF37H |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 42/79頁 |
| 文件大?。?/td> | 1028K |
| 代理商： | V59C1G01808QAUF37H |
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ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
Concurrent Auto-Precharge
DDR2 devices support the “concurrent Auto-Precharge” feature. A read with Auto-Precharge enabled, or a
write with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that com-
mand does not interrupt the read or write data transfer, and all other related limitations (e.g. contention
between Read data and Write data must be avoided externally and on the internal data bus.
The minimum delay from a read or write command with Auto-Precharge enabled, to a command to a different
bank, is summarized in the table below. As defined, the WL = RL - 1 for DDR2 devices which allows the com-
mand gap and corresponding data gaps to be minimized.
From Command
To Command
(different bank,
non-interrupting command)
Minimum Delay with
Concurrent Auto-Pre-
charge Support
Units
WRITE w/AP
Read or Read w/AP
(CL -1) + (BL/2) + tWTR
tCK
Write ot Write w/AP
BL/2
tCK
Precharge or Activate
1
tCK
Read w/AP
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
BL/2 + 2
tCK
Precharge or Activate
1
tCK
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