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參數(shù)資料
| 型號： | V6118 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2, 4 and 8 Multiplex LCD Driver |
| 中文描述： | 2，4和8復(fù)用LCD驅(qū)動器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 465K |
| 代理商： | V6118 |
10
Functional Description
Supply Voltage V
, V
, V
LCD
DD
and V
SS
The voltage between V
logicandtheinterface.ThevoltagebetweenV
supply voltage for the LCD and is used for the generation of the
internal LCD bias levels. The internal LCD bias levels have a
maximum impedance of 25 k
Without external connections to the V1, V2, and V3 bias level
inputs,theV6118 candrivemostmediumsizedLCD (pixel area
upto4'000 mm ).
Fordisplays with a widevariationinpixel sizes the configuration
shown in Fig. 13 can give enhanced contrast by giving faster
pixel switching times. On changing the row polarity (see Fig. 7,
8and 9 ) the parallelcapacitorslower theimpedance ofthe bias
level generation to the peak current, giving faster pixel charge
times and thus a higher RMS "on" value. A higher RMS "on"
value can give better contrast. If for a given LCD size and
operating voltage, the "off" pixels appear "on", or there is poor
contrast, then an external bias level generation circuit can be
used with the V 6118. An external bias level generation circuit
canlowerthebias levelimpedance andhence improvetheLCD
contrast (see Fig.12). The optimum values ofR, Rx, and C,vary
according to the LCD size used and V
determinedthroughactualexperimentationwiththeLCD.
For LCD with every large average pixel size up to 10'000 mm ,
thebiaslevelconfigurationshowninFig.14shouldbeused.
When V 6118s are cascaded connect the V1, V2, and V3 bias
inputsareshowninFig.10.Thepixelloadisaveragedacrossall
the cascaded drivers. This will give enhanced display contrast
as the effective bias level source impedance is the parallel
combination of the total number of drivers. For example, if two
V 6118 are cascaded as shown in Fig. 10, then the maximum
bias level impedance becomes 12.5 K
3 to 8 V. Table 8 shows the relationship between V1, V2, and V3
for multiplex rates 2, 4 and 8. Note that V
the
V 6118 2 and
V 6118 8, and for the
V
>V1>V2.
LCD
is the supply voltage for the
andV
isthe
for a V
voltage from 3 to 8 V.
. They are best
for a V
voltage from
>V1>V2>V3 for
V 6118 4,
Thedata inputpin,DI,is usedto loadserialdata into the V 6118.
Theserialdata word lengthis 40 bits when
48 bits when it is active. Data is loaded in inverse numerical
order, the data for bit 40 (bit 48 when
first with the data for bit 1 last. The column data bits are loaded
firstandthentheaddressbits(seeFig.4and 5).
The data output pin, DO, is used in cascaded applications (see
Fig. 10). DO transfers the data to the next cascaded chip. The
dataatDOisequaltothedataatDIdelayedby40clockperiods,
when
isinactiveand48clockperiodswhen
Inorder to cascadeV6118s,DOofonechipmustbeconnected
to DI of the following chip (see Fig. 10). In cascaded
applications the data of the last V 6118 (the one that does not
have DO connected) must be loaded first and the data for the
first V6118 (its DI is connected to the processor) loaded last
(seeFig.10).
is inactive,and
is active) is loaded
isactive.
DD
SS
LCD
SS
LCD
LCD
LCD
LCD
2
DataInput/Output
COL
COL
COL
COL
The display RAM word length is 40 bits (see Fig. 6). Each LCD
row has a corresponding display RAM address which provides
the column data (on or off) whenthe rowis selected (on). When
down loading data to the V 6118 any display RAM address can
be chosen, there is no display RAM addressing sequence (see
Fig.4 and 5).
The same data can be written to more than one display RAM
address. Ifmorethanoneaddressbitisset,then more thanone
display RAM address is write enabled, and so the same data is
written to more than one address. This feature can be useful to
flash the LCD on and off under software control. If the address
bits are all zero then no display RAM is write enabled and no
data is written to the display RAM on the falling edge of STR.
Use address 0 to synchronize cascaded V 6118s without
updatingthedisplayRAM.
LCD, and synchronize cascaded V 6118s. The STR input writes
the data loaded into the shift register, on the DI input, to the
display RAM on the falling edge of the STR signal. The display
RAMaddressisgivenbytheaddressbits(seeFig.4and5).
The STR input when high blanks the LCD by disconnecting the
internal voltage bias generation from the V
Segment outputs S1 to S40 (rows and columns) are pulled up
to V
. The delay to driving the LCD with V
dependent on the capacitive load of the LCD and is typically 1
μs. An LCD pixel responds to RMS voltage and takes
approximately 100 ms to turn on or off. The delay from putting
STR high to the LCD being blank is dependent on the LCD off
time and is typically 100 ms. In applications, which have a long
STR pulse width (10 μs), the LCD is driven by V
rowsandcolumnsduringthis time. Asthe timeis short(1μA),it
will have zero measurable effect on the RMS "on" value (over
100 ms) of an LCD pixel and also zero measurable effect on the
pixel DC component. Such STR pulses will not be visible to the
humaneyeonanLCD.
potential.
on S1 to S40, is
on both the
When STR is high the LCD will be
driven by the parallel combination of the external voltage bias
generation circuit and part of the internal voltage bias
generationcircuit.
The STR input, when high, synchronizes cascaded V 6118s by
forcinganewtimeframetobeginatthenextfalling edge of the
FR input signal (see Fig.6). A time frame begins withrow1
and so the LCD picture is rebuilt from row 1 each time
CLK Input
The CLK is used to clock the DI serial data into the shift register
and to clock the DO serial data out.Loading andshiftingofdata
occurs at the falling edge of this clock, outputting of the data at
the rising edge (see Fig. 3). When cascading devices, all CLK
linesshouldbetiedtogether(seeFig.10).
STR Input
The STR input is used to write to the display RAM, blank the
SS
LCD
LCD
LCD
Note if an external voltage bias generation circuitis usedas
shown in Fig. 12 and 14, the LCD blank function (STR high)
will not blank the LCD.
V6118 2/4/8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V61188TAB | 2, 4 and 8 Multiplex LCD Driver |
| V6118852F | 2, 4 and 8 Multiplex LCD Driver |
| V61188 | 2, 4 and 8 Multiplex LCD Driver |
| V61184TAB | 2, 4 and 8 Multiplex LCD Driver |
| V6118452F | 2, 4 and 8 Multiplex LCD Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V61182 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2, 4 and 8 Multiplex LCD Driver |
| V6118252F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2, 4 and 8 Multiplex LCD Driver |
| V61182TAB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2, 4 and 8 Multiplex LCD Driver |
| V61184 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2, 4 and 8 Multiplex LCD Driver |
| V6118452F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2, 4 and 8 Multiplex LCD Driver |
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