參數(shù)資料
型號: V61C3181024
廠商: Mosel Vitelic, Corp.
英文描述: 128K X 8 HIGH SPEED STATIC RAM
中文描述: 128K的乘八高速靜態(tài)RAM
文件頁數(shù): 6/10頁
文件大小: 77K
代理商: V61C3181024
6
V61C3181024 Rev. 1.3 February 1999
MOSEL V ITELIC
V61C3181024
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Write Cycle
Parameter
Name
Parameter
-10
-12
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
t
RC
Read Cycle Time
10
12
15
ns
t
AA
Address Access Time
10
12
15
ns
t
ACS1
Chip Enable Access Time
10
12
15
ns
t
ACS2
Chip Enable Access Time
10
12
15
ns
t
OE
Output Enable to Output Valid
6
6
7
ns
t
CLZ1
Chip Enable to Output in Low Z
3
3
3
ns
t
CLZ2
Chip Enable to Output in Low Z
3
3
3
ns
t
OLZ
Output Enable to Output in Low Z
0
0
0
ns
t
CHZ
Chip Disable to Output in High Z
0
3
0
3
0
4
ns
t
OHZ
Output Disable to Output in High Z
0
3
0
3
0
4
ns
t
OH
Output Hold from Address Change
3
3
3
ns
Parameter
Name
Parameter
-10
-12
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
t
WC
Write Cycle Time
10
12
15
ns
t
CW1
Chip Enable to End of Write
8
10
13
ns
t
CW2
Chip Enable to End of Write
8
10
13
ns
t
AS
Address Setup Time
0
0
0
ns
t
AW
Address Valid to End of Write
8
10
13
ns
t
WP
Write Pulse Width
8
9
11
ns
t
AH
Address Hold to End of Write
0
0
0
ns
t
WHZ
Write to Output High-Z
0
5
0
5
0
5
ns
t
WLZ
Write to Output Low Z
3
3
5
ns
t
DW
Data Setup to End of Write
5
6
8
ns
t
DH
Data Hold from End of Write
0
0
0
ns
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