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參數資料
| 型號： | V61C5181024 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128K X 8 HIGH SPEED STATIC RAM |
| 中文描述： | 128K的乘八高速靜態(tài)RAM |
| 文件頁數： | 2/12頁 |
| 文件大?。?/td> | 61K |
| 代理商： | V61C5181024 |
2
V61C5181024 Rev. 1.1 July 1998
MOSEL V ITELIC
V61C5181024
Pin Descriptions
A
These 17 address inputs select one of the 128K x 8
bit segments in the RAM.
0
–A
16
Address Inputs
CE
CE
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
1
1
, CE
is active LOW and CE
2
Chip Enable Inputs
2
is active HIGH. Both
OE
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
Output Enable Input
WE
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
Write Enable Input
I/O
These 8 bidirectional ports are used to read data
from and write data into the RAM.
0
–I/O
7
Data Input and Data Output Ports
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
32-Pin SOJ
32-Pin TSOP-I (Standard)
1
32
5181024 02
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
NC
A
11
CE
2
WE
A
12
A
13
A
14
A
15
OE
A
16
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3181024 03
A15
A14
A13
A12
WE
A11
VCC
NC
A10
A9
A8
A7
A6
A5
A4
A16
CE1
CE2
I/O6
I/O5
I/O4
I/O3
VSS
I/O7
OE
I/O0
A0
A1
A2
A3
I/O1
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