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參數(shù)資料
| 型號： | V61C518256-10R |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K X 8 HIGH SPEED STATIC RAM |
| 中文描述： | 32K的乘八高速靜態(tài)RAM |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 70K |
| 代理商： | V61C518256-10R |
MOSEL V ITELIC
V61C518256
5
V61C518256 Rev. 0.3 July 1998
Data Retention Characteristics
NOTES:
1.
2.
t
T
RC
A
= Read Cycle Time
= +25
°
C.
Low V
CC
Data Retention Waveform
Symbol
Parameter
Min.
Typ.
(2)
Max.
Units
V
DR
V
CC
for Data Retention
CE
3
V
CC
– 0.2V
2.0
—
5.5
V
I
CCDR
Data Retention Current
V
DR
= 3.0V, CE
3
V
DR
– 0.2V
Com’l
—
—
150
m
A
Ind.
—
—
200
t
CDR
Chip Deselect to Data Retention Time
0
—
—
ns
t
R
Operation Recovery Time (see Retention Waveform)
t
RC(1)
—
—
ns
V
CC
518256-07
Data Retention Mode
V
DR
CE
2.2V
2.2V
4.5V
t
CDR
t
R
V
DR
3
2V
4.5V
AC Test Conditions
AC Test Loads and Waveforms
Key to Switching Waveforms
Input Pulse Levels
0 to 3V
Input Rise and Fall Times
3 ns
Timing Reference Levels
1.5V
Output Load
see below
+5V
480
480
255
* Includes scope and jig capacitance
+5V
I/O Pin
C
L
= 30 pF*
255
Output load for t
CLZ
, t
CHZ
, t
OHZ
, t
OLZ
, t
WZ
, t
OW
I/O Pin
5 pF*
518256-06
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
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