參數(shù)資料
型號: V62C1161024L-120T
廠商: Mosel Vitelic, Corp.
英文描述: TRANS PNP 100VCEO 5A TO-220F
中文描述: 超低功耗64K的× 16 CMOS SRAM的
文件頁數(shù): 5/10頁
文件大?。?/td> 119K
代理商: V62C1161024L-120T
Timing Waveform of Read Cycle 1
(Address Controlled)
t
RC
t
AA
t
OH
Data Valid
Address
Data Out
Timing Waveform of Read Cycle 2
t
OHZ
t
RC
t
OLZ
t
ACE
t
LZ(4,5)
t
BA
CE
Previous Data Valid
Address
t
OH
t
AA
t
OE
t
BLZ(4,5)
t
BHZ(3,4,5)
t
HZ(3,4,5)
(BLE/BHE)
OE
Data Out
Data Valid
High-Z
V62C1161024L(L)
5
Notes
(Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition
t
HZ
(max.) is less than
t
LZ
(min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = V
IL
.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see
AC Test Condition
, Figure A.
REV. 1.
1
April
2001 V62C1
161024
L(L)
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