參數(shù)資料
型號(hào): V62C1162048L(L)-100B
廠商: Mosel Vitelic, Corp.
英文描述: Ultra Low Power 128K x 16 CMOS SRAM
中文描述: 128K的超低功耗× 16 CMOS SRAM的
文件頁(yè)數(shù): 5/11頁(yè)
文件大?。?/td> 109K
代理商: V62C1162048L(L)-100B
V62C1162048L(L)
Parameter
Sym
Unit
Note
Read Cycle Time
t
RC
70
-
85
-
100
-
120
-
ns
Address Access Time
t
AA
-
70
-
85
-
100
-
120
ns
Chip Enable Access Time
t
ACE
-
70
-
85
-
100
-
120
ns
Output Enable Access Time
t
OE
-
40
-
40
-
50
-
60
ns
Output
Hold from
Address Change
t
OH
10
-
10
-
10
-
10
-
ns
Chip Enable to Output in Low-Z
t
LZ
10
-
10
-
10
-
10
-
ns
4,5
Chip Disable to Output in High-Z
t
HZ
-
30
-
35
-
40
-
45
ns
3,4,5
Output Enable to Output in Low-Z
t
OLZ
5
-
5
-
5
-
5
-
ns
Output
Disable to
Output in High-Z
t
OHZ
-
25
-
30
-
35
-
40
ns
BLE, BHE Enable to Output in Low-Z
t
BLZ
5
-
5
-
5
-
5
-
ns
4,5
BLE, BHE Disable to Output in High-Z
t
BHZ
-
25
-
30
-
35
-
40
ns
3,4,5
BLE, BHE Access Time
t
BA
-
40
-
40
-
50
-
60
ns
Read Cycle
(9)
(V
cc
= 1.8 to 2.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Write Cycle
(11)
(V
cc
= 1.8 to 2.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Parameter
Symbol
Unit
Note
Write Cycle Time
t
WC
70
-
85
-
100
-
120
-
ns
Chip Enable to Write End
t
CW
60
-
70
-
80
-
90
-
ns
Address Setup to Write End
t
AW
60
-
70
-
80
-
90
-
ns
Address Setup Time
t
AS
0
-
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
50
-
60
-
70
-
80
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
0
-
ns
Data Valid to Write End
t
DW
30
-
35
-
40
-
45
-
ns
Data Hold Time
t
DH
0
-
0
-
0
-
0
-
ns
Write Enable to Output in High-Z
t
WHZ
-
30
-
35
-
40
-
45
ns
Output Active fromWrite End
t
OW
5
-
5
-
5
-
5
-
ns
BLE, BHE Setup to Write End
t
BW
60
-
70
-
80
-
90
-
ns
Min Max Min Max Min Max Min Max
-70
-85
-100
-120
5
Min Max Min Max Min Max Min Max
-70
-85
-100
-120
REV. 1.
2
May
2001 V62C
1
16
20
48
L(L)
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