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參數(shù)資料
| 型號(hào)： | V62C1802048L-100V |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 8 STANDARD SRAM, 100 ns, PDSO32 |
| 封裝： | 8 X 13.40 MM, PLASTIC, STSOP-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 84K |
| 代理商： | V62C1802048L-100V |
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5
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7
8
9
16
15
14
13
12
11
10
A8
A9
A11
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
32
31
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29
28
27
26
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24
17
18
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20
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23
CE1
A10
OE
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
Cell Array
ROW
DECODER
SENSE
AMP
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
I/O8
I/O1
OE
WE
CE1
CE2
A8
A7
A6
A5
A4
A3
A2
A1
A0
A9
A10
A11
A12
A13
A14
A15
A16
A17
V62C1802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
Low-power consumption
- Active: 25mA at 70ns
- Stand-by: 10
A (CMOS input/output)
2
A CMOS input/output, L version
Single + 1.8 to 2.2V Power Supply
Equal access and cycle time
70/85/100/150 ns access time
Easy memory expansion with CE1, CE2
and OE inputs
1.0V data retention mode
TTL compatible, Tri-state input/output
Automatic power-down when deselected
Package available: 32-TSOP1 / STSOP
Functional Description
The V62C1802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1 , an active HIGH CE2, an act-
ive LOW OE , and Tri-state I/O’s. This device has an auto-
matic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1) with Write Enable (WE) LOW, and Chip En-
able 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1) with Output Enable
(OE ) LOW while Write Enable (WE ) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-imped-
ance state when the device is deselected: the outputs are
disabled during a write cycle.
The V62C1802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1802048L is available in
a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.
32-Pin TSOP1 / STSOP
Logic Block Diagram
REV. 1.2 May 2001 V62C1802048L(L)
1
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