參數(shù)資料
型號: V62C18161024
廠商: Mosel Vitelic, Corp.
英文描述: 1.8 Volt 128K x 16 Static RAM(1.8V 128Kx16靜態(tài)RAM)
中文描述: 1.8伏128K的× 16靜態(tài)RAM(1.8 128Kx16靜態(tài)內(nèi)存)
文件頁數(shù): 6/10頁
文件大?。?/td> 61K
代理商: V62C18161024
6
V62C18161024 Rev. 0.1 February 1999
MOSEL V ITELIC
V62C18161024
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Write Cycle
Parameter
Name
Parameter
90
120
Unit
Min.
Max.
Min.
Max.
t
RC
Read Cycle Time
90
120
ns
t
AA
Address Access Time
90
120
ns
t
ACS
Chip Enable Access Time
90
120
ns
t
BA
UBE, LBE Access Time
40
50
ns
t
OE
Output Enable to Output Valid
40
50
ns
t
CLZ
Chip Enable to Output in Low Z
10
10
ns
t
BLZ
UBE, LBE to Output in Low Z
10
10
ns
t
OLZ
Output Enable to Output in Low Z
10
10
ns
t
CHZ
Chip Disable to Output in High Z
0
35
0
40
ns
t
OHZ
Output Disable to Output in High Z
0
30
0
35
ns
t
BHZ
UBE, LBE to Output in High Z
0
30
0
35
ns
t
OH
Output Hold from Address Change
10
10
ns
Parameter
Name
Parameter
90
120
Unit
Min.
Max.
Min.
Max.
t
WC
Write Cycle Time
90
120
ns
t
CW
Chip Enable to End of Write
75
100
ns
t
AS
Address Setup Time
0
0
ns
t
AW
Address Valid to End of Write
75
75
ns
t
WP
Write Pulse Width
65
95
ns
t
WR
Write Recovery Time
0
0
ns
t
WHZ
Write to Output High-Z
0
35
0
40
ns
t
WLZ
Write to Output Low Z
10
15
ns
t
DW
Data Setup to End of Write
35
40
ns
t
DH
Data Hold from End of Write
0
0
ns
t
BW
UBE, LBE to End of Write
70
80
ns
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