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參數(shù)資料
| 型號(hào)： | V62C1881024 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 1.8 Volt 128K X 8 Static RAM(1.8V 128Kx8靜態(tài)RAM) |
| 中文描述： | 1.8伏128K的× 8靜態(tài)RAM（1.8 128Kx8靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 62K |
| 代理商： | V62C1881024 |
2
V62C1881024 Rev. 0.2 February 1999
MOSEL V ITELIC
V62C1881024
Pin Descriptions
A
These 17 address inputs select one of the 128K x 8
bit segments in the RAM.
0
–A
16
Address Inputs
CE
CE
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
1
1
, CE
is active LOW and CE
2
Chip Enable Inputs
2
is active HIGH. Both
OE
The output enable input is active LOW. When OE is
LOW with CE LOW and WE HIGH, data of the
selected memory allocation will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
Output Enable Input
WE
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be written
into the selected memory location.
Write Enable Input
I/O
These 8 bidirectional ports are used to read data
from and write data into the RAM.
0
–I/O
7
Data Input and Data Output Ports
V
CC
Power Supply
GND
Ground
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O43
GND
I/O2
I/O1
I/OO
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1881024-02
32-PIN TSOP/STSOP
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