- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202173 > V62C2162048LL-100T (MOSEL-VITELIC) 128K X 16 STANDARD SRAM, 100 ns, PDSO44 PDF資料下載
參數(shù)資料
| 型號： | V62C2162048LL-100T |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 STANDARD SRAM, 100 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 117K |
| 代理商： | V62C2162048LL-100T |
Memory Array
1024 X 2048
Row
Select
I/O Circuit
Pre-Charge Circuit
Column Select
Data
Cont
Data
Cont
Vcc
Vss
A10 A11 A12 A13 A14
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
A15 A16
V62C2162048L(L)
Ultra Low Power
128K x 16 CMOS SRAM
Features
Low-power consumption
- Active: 65mA ICC at 35ns
- Stand-by: 10
A (CMOS input/output)
2
A (CMOS input/output, L version)
35/45/55/70/85/100 ns access time
Equal access and cycle time
Single +2.2V to 2.7V Power Supply
Tri-state output
Automatic power-down when deselected
Multiple center power and ground pins for
improved noise immunity
Individual byte controls for both Read and
Write cycles
Available in 44 pin TSOP II / 48-fpBGA
Functional Description
The V62C2162048L is a Low Power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
memory expansion is provided by an active LOW (CE)
and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
TSOPII / 48-fpBGA
Logic Block Diagram
1
2
3
12
10
11
8
39
13
9
7
6
4
5
26
25
24
23
22
21
14
15
16
17
18
19
20
40
41
42
43
44
38
37
36
35
34
33
32
31
30
29
28
27
A9
A8
A7
A6
A5
A4
A3
A2
A1
WE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0
CE
Vss
Vcc
A12
A16
A15
A14
A13
A11
A10
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
NC
Vss
Vcc
BHE
BLE
OE
REV. 1.3 OCT 2001 V62C2162048L(L)
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V62C2162048L-45T | 128K X 16 STANDARD SRAM, 45 ns, PDSO44 |
| V62C2801024LL-100B | 128K X 8 STANDARD SRAM, 100 ns, PBGA48 |
| V62C3161024L-55T | 64K X 16 STANDARD SRAM, 55 ns, PDSO44 |
| V62C3162096L-35BI | 128K X 16 STANDARD SRAM, 35 ns, PBGA48 |
| V62C3162096L-85BI | 128K X 16 STANDARD SRAM, 85 ns, PBGA48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V62C2162048LL-35B | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 128K x 16 CMOS SRAM |
| V62C2162048LL-35T | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 128K x 16 CMOS SRAM |
| V62C2162048LL-45B | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 128K x 16 CMOS SRAM |
| V62C2162048LL-45T | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 128K x 16 CMOS SRAM |
| V62C2162048LL-55B | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 128K x 16 CMOS SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。