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參數(shù)資料
| 型號： | V62C2184096 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 512K X 8, CMOS STATIC RAM |
| 中文描述： | 為512k × 8，的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 49K |
| 代理商： | V62C2184096 |
2
V62C2184096 Rev. 1.5 June 2000
MOSEL VITELIC
V62C2184096
Pin Descriptions
A
These 19 address inputs select one of the 512K x 8
bit segments in the RAM.
0
–A
18
Address Inputs
CE
CE
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
1
1
, CE
is active LOW and CE
2
* Chip Enable Inputs
2
is active HIGH. Both
OE
The Output Enable input is active LOW. With chip
enabled, when OE is LOW and WE HIGH, data of
the selected memory location will be available on
the I/O pins. When OE is HIGH, the I/O pins will be
in the high impedance state.
Output Enable Input
WE
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
Write Enable Input
I/O
These 8 bidirectional ports are used to read data
from and write data into the RAM.
1
–I/O
8
Data Input and Data Output Ports
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
32-Pin TSOP (Standard)
36 BGA
A11
A9
A8
A13
WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
1
2
3
4
5
6
1
Note:
NC means no connect.
NB means no ball.
2
TOP VIEW
TOP VIEW
3
4
5
6
B
C
D
E
F
G
H
A
A0
I/O5
I/O6
B
C
D
E
F
G
H
VSS
VCC
I/O7
I/O8
A9
A1
A2
NB
NB
NB
NB
OE
A10
CE2
WE
NC
NB
NB
A18
CE1
A11
A3
A4
A5
NB
NB
A17
A16
A12
A6
A7
NB
NB
NB
NB
A15
A13
A8
I/O1
I/O2
VCC
VSS
I/O3
I/O4
A14
*CE
2
is available on BGA package only.
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