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參數(shù)資料
| 型號(hào)： | V62C2802048LL-55T |
| 廠商： | Mosel Vitelic, Corp. |
| 元件分類： | SRAM |
| 英文描述： | Ultra Low Power 256K x 8 CMOS SRAM |
| 中文描述： | 超低功耗256K × 8 CMOS SRAM的 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 94K |
| 代理商： | V62C2802048LL-55T |
V62C2802048L(L)
Data Retention Characteristics
(L Version Only)
(1)
Parameter
Symbol
Test Condition
Min
Max
Unit
V
CC
for Data Retention
V
DR
CE
1
> V
CC
- 0.2V or
1.0
-
V
Data Retention Current
I
CCDR
CE
2
< + 0.2V
-
1
μ
A
Chip Deselect to Data Retention Time
t
CDR
V
IN
> V
CC
- 0.2V or
0
-
ns
Operation Recovery Time
(2)
t
R
V
IN
< 0.2V
t
RC
-
ns
Data Retention Mode
V
DR
>
1.0V
Vcc Typ
V
IH
V
IH
V
DR
V
CC
CE
t
R
t
CDR
Vcc Typ
Data Retention Waveform
(L Version Only) (T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
8
Notes
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see
AC Test Condition
, Figure A.
4. This parameter is tested with CL = 5
p
F as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
REV. 1.
2
May
2001 V62C
2
8020
48
L(L)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| V62C2802048LL-70T | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 256K x 8 CMOS SRAM |
| V62C2802048LL-85T | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 256K x 8 CMOS SRAM |
| V62C2804096 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:512K X 8, CMOS STATIC RAM |
| V62C3161024L | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 64K x 16 CMOS SRAM |
| V62C3161024L-100T | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:Ultra Low Power 64K x 16 CMOS SRAM |
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