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參數(shù)資料
| 型號(hào)： | V62C3162096L-35BI |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 STANDARD SRAM, 35 ns, PBGA48 |
| 封裝： | 9 X 12 MM, FBGA-48 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 114K |
| 代理商： | V62C3162096L-35BI |
8
Notes (Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3.
t
HZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels.
4. At any given temperature and voltage condition
t
HZ (max.) is less than tLZ (min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = VIL.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see AC Test Condition, Figure A.
Timing Waveform of Read Cycle 1 (Address Controlled)
t
RC
t
AA
t
OH
Data Valid
Address
Data Out
Timing Waveform of Read Cycle 2
t
OHZ
t
RC
t
OLZ
t
ACE
t
LZ(4,5)
CE
Previous Data Valid
Address
t
OH
t
AA
t
OE
t
BA
t
BLZ(4,5)
t
BHZ(3,4,5)
t
HZ(3,4,5)
(BLE/BHE)
OE
Data Out
Data Valid
V62C3162096L(L)
REV. 1.1 April 2001 V62C3162096L(L)
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