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參數(shù)資料
| 型號： | V62C3184096L-55T |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | TSOP-32 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 52K |
| 代理商： | V62C3184096L-55T |
8
V62C3184096 Rev. 1.1 June 2000
MOSEL V ITELIC
V62C3184096
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)
(4, 7)
Write Cycle 2 (CE Controlled)
(4, 7)
NOTES:
1.
The internal write time of the memory is defined by the overlap of CE
1
and CE
2
active and WE low. All signals must be active to
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
t
WR
is measured from the earlier of CE
1
or WE going high, or CE
2
going LOW at the end of the write cycle.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
OE = V
IL
or V
IH
. However it is recommended to keep OE at V
IH
during write cycle to avoid bus contention.
If CE
1
is LOW and CE
2
is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
t
CW
is measured from CE
1
going low or CE
2
going HIGH to the end of write.
CE
2
is offered on BGA package only.
2.
3.
4.
5.
6.
7.
ADDRESS
OUTPUT
INPUT
CE
1
CE
2
WE
t
WC
t
CW(6)
t
CW(6)
t
DW
t
DH
t
AW
t
WR(2)
t
WHZ
t
WP(1)
t
AS
ADDRESS
OUTPUT
High-Z
INPUT
CE
1
CE
2
WE
t
WC
t
DW
t
DH
t
AW
t
CW(6)
t
CW(6)
t
WR(2)
t
AS
(4)
(5)
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