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參數(shù)資料
| 型號： | V63C31321024 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K X 32 CMOS Synchronous Burst Pipelined SRAM(32Kx32CMOS同步脈沖流水線式SRAM) |
| 中文描述： | 32K的× 32的CMOS SRAM的同步突發(fā)流水線（32Kx32CMOS同步脈沖流水線式的SRAM） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 119K |
| 代理商： | V63C31321024 |
MOSEL V ITELIC
V63C31321024
6
V63C31321024 Rev. 0.3 February 1999
Write Mode
The V63C31321024 support different kinds of
write mode operations. The BWE and BW [3:0]
support individual byte writes. The BE [7:0] signals
can be directly connected to the SRAM BW [3:0].
The GW signal is used to override the byte enable
signals and allows the cache controller to write all
bytes to the SRAM, no matter what the byte write
enable signals are. The various write modes are
indicated in the Write Table, below. Note that in
pipelined mode, the byte write enable signals are
not latched by the SRAM with addresses but with
data. In pipelined mode, the cache controller must
ensure the SRAM latches both data and valid byte
enable signals from the processor.
Write Table
Burst Address Sequence
Read/Write Function
GW
BWE
BW3
BW2
BW1
BW0
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0, I/O
0
– I/O
7
1
0
1
1
1
0
Write Byte 1, I/O
8
– I/O
15
1
0
1
1
0
1
Write Byte 1, Byte 0
1
0
1
1
0
0
Write Byte 2, I/O
16
– I/O
23
1
0
1
0
1
1
Write Byte 2, Byte 0
1
0
1
0
1
0
Write Byte 2, Byte 1
1
0
1
0
0
1
Write Byte 2, Byte 1, Byte 0
1
0
1
0
0
0
Write Byte 3, I/O
24
– I/O
31
1
0
0
1
1
1
Write Byte 3, Byte 0
1
0
0
1
1
0
Write Byte 3, Byte 1
1
0
0
1
0
1
Write Byte 3, Byte 1, Byte 0
1
0
0
1
0
0
Write Byte 3, Byte 2
1
0
0
0
1
1
Write Byte 3, Byte 2, Byte 0
1
0
0
0
1
0
Write Byte 3, Byte 2, Byte 1
1
0
0
0
0
1
Write All Bytes, I/O
0
– I/O
31
1
0
0
0
0
0
Write All Bytes, I/O
0
– I/O
31
0
X
X
X
X
X
Intel System (LBO = V
CCQ
)
Linear Mode (LBO = GNDQ)
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
External Start Address
00
01
10
11
00
01
10
11
Second Address
01
00
11
10
01
10
11
00
Third Address
10
11
00
01
10
11
00
01
Fourth Address
11
10
01
00
11
00
01
10
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