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參數(shù)資料
| 型號： | V63C31322048 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 64K X 32 CMOS Synchronous Burst Pipelined SRAM(64Kx32CMOS同步脈沖流水式SRAM) |
| 中文描述： | 64K的× 32的CMOS SRAM的同步突發(fā)流水線（64Kx32CMOS同步脈沖流水式的SRAM） |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 120K |
| 代理商： | V63C31322048 |
MOSEL V ITELIC
V63C31322048
4
V63C31322048 Rev. 0.2 February 1999
Absolute Maximum Ratings*
Core Supply Voltage to GND.............–0.5 to +4.6V
I/O Supply Voltage to GND................–0.5 to +4.6V
Input/Output to
GND Potential......... GNDQ–0.5 to V
Allowable Power Dissipation ..........................1.0W
Storage Temperature ...................... –65 to +150
Operating Temperature ......................... 0 to +70
CCQ
+0.5V
°
°
C
C
Note:
Exposure to conditions beyond those listed under
Absolute Maximum Ratings
and reliability of the device.
may adversely affect the life
Capacitance
V
CC
= 3.3 V, T
A
= 25
°
C, f = 1 MHz
* Note: These parameters are guaranteed by device
characterization and are not production tested.
Symbol
Parameter*
Conditions Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
I/O
Input/Output
Capacitance
V
OUT
= 0V
8
pF
Pin Names
Symbol
Type
Description
A0—A15
Input, Synchronous
Address
I/O
0
-I/O
31
I/O, Synchronous
Data Inputs/Outputs
CLK
Input, Clock
Processor Host Bus Clock
CE1, CE2, CE3
Input, Synchronous
Chip Enables
GW
Input, Synchronous
Global Write
BWE
Input, Synchronous
Byte Write Enable from Cache Controller
BW
0
-BW
3
Input, Synchronous
Host BusByte Enables Used with BWE
OE
Input, Asynchronous
Output Enable
ADV
Input, Synchronous
Internal Burst Address Counter Advance
ADSC
Input, Synchronous
Address Status from Controller
ADSP
Input, Synchronous
Address Status from Processor
ZZ
Input, Asynchronous
Snooze Pin for Low-Power State
LBO
Input, Static
This Mode Selects Burst Sequence; LOW for Linear, HIGH for interleaved
V
CCQ
I/O Power Supply
GNDQ
I/O Ground
V
CC
Power Supply
GND
Ground
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