參數(shù)資料
型號(hào)： VC-801-JAE-KABN-13M5000000
廠商： VECTRON INTERNATIONAL
元件分類： XO, clock
英文描述： CRYSTAL OSCILLATOR, CLOCK, 13.5 MHz, CMOS OUTPUT
封裝： ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-4
文件頁(yè)數(shù)： 2/8頁(yè)
文件大?。?/td> 0K
代理商： VC-801-JAE-KABN-13M5000000
Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 http://www.vectron.com
Page2
Performance Specifications
Table 1. Electrical Performance, 5V Option
Parameter
Symbol
Min
Typical
Maximum
Units
Supply
Voltage1
V
DD
4.5
5.0
5.5
V
Max Voltage
-0.7
7
V
Current2
≤20.000MHz
20.001 to 50.000MHz
50.001 to 75.000MHz
I
DD
10
30
40
mA
Current, Output Disabled
30
uA
Frequency
Nominal Frequency3
f
N
1.544
75.000
MHz
Stability4, (Ordering Option)
±20, ±25, ±32, ±50, ±100
ppm
Outputs
Output Logic Levels2
Output Logic High
Output Logic Low
Output Logic High Drive
Output Logic Low Drive
V
OH
V
OL
I
OH
I
OL
0.9*V
DD
16
0.1*V
DD
V
mA
Load
I
OUT
15
pF
Output Rise /Fall Time2
<20.000MHz
20.000 to 50.000MHz
50.001 to 75.000MHz
t
R
/t
F
8
5
2
ns
Output Leakage, Output Disabled
I
Z
±10
uA
Duty Cycle2,5
45
50
55
%
Period Jitter6
RMS
Peak-Peak
фJ
3.0
21
ps
RMS Jitter, 12k-20MHz
фJ
0.5
1
ps
Enable/Disable
Output Enable/Disable7
Output Enable
Output Disable
V
IH
V
IL
4.0
0.8
V
Disable time
t
D
100
ns
Enable Internal Pull-Up Resistor
100
Kohm
Start-Up Time
t
SU
8ms
Operating Temp, (Ordering Option)
T
OP
-10/70 or -40/85
°C
The power supply should have by-pass capacitors as close to the supply and to ground as possible, for example 0.1 and 0.01uF.
1]
Parameters are tested with production test circuit below , Figure 1.
2]
See Standard Frequencies and Ordering Information tables for more specific information.
3]
Includes initial accuracy, operating temperature, supply voltage, shock and vibration (not under operation) and aging for 50 and 100ppm options.
4]
Duty Cycle is measured as On Time/Period (Fig 2).
5]
Broadband Period Jitter measured using Wavecrest SIA3300C, 90K samples, see Application Note for Typical Phase Noise and Jitter Performance.
6]
The Output is Enabled if the Enable/Disable is left open.
7]
I
DD
V
DD
15pF
4
12
3
.1μF
.01μF
+
t
R
t
F
V
OH
V
OL
50%
On Time
Period
Fig 2: Waveform
Fig 1: Test Circuit
Specifications
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