參數(shù)資料
型號: VC16240ADL
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 16-bit buffer/line driver; inverting 3-State
中文描述: LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48
封裝: 7.50 MM, PLASTIC, SOT-370-1, SSOP3-48
文件頁數(shù): 2/10頁
文件大?。?/td> 78K
代理商: VC16240ADL
Philips Semiconductors
Product specification
74LVC16240A
16-bit buffer/line driver; inverting (3-State)
2
1997 Jul 29
853-2007 18218
FEATURES
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
DESCRIPTION
The 74LVC16240A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families. Inputs can be driven from either 3.3V or 5V
devices. In 3-State operation, outputs can handle 5V. These
features allow the use of these devices in a mixed 3.3V/5V
environment.
The 74LVC16240A is a 16-bit inverting buffer/line driver with
3-State outputs. The 3-State outputs are controlled by the output
enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to
assume a high impedance OFF-state.
The 74LVC16240A is identical to the 74LVC16244A but has
inverting outputs.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
2Y0
3Y2
3Y3
V
CC
4Y0
4Y1
4A1
4A0
V
CC
3A3
3A2
GND
3A1
3A0
2A3
2A2
GND
2A1
2A0
V
CC
1A3
1A2
GND
1A1
1A0
2OE
21
22
23
24
25
26
27
28
GND
4Y2
4Y3
4OE
3OE
4A3
4A2
GND
SW00041
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 C; t
r
= t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
1An to 1Yn;
2An to 2Yn
C
L
= 50pF
V
CC
= 3.3V
2.7
ns
C
I
Input capacitance
Power dissipation capacitance per
buffer
5.0
pF
C
PD
V
CC
= 3.3V
25
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
= C
PD
x V
CC2
x f
i
+ (C
L
x V
CC2
x f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
x V
CC2
x f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74LVC16240A DL
74LVC16240A DGG
NORTH AMERICA
VC16240A DL
VC16240A DGG
DWG NUMBER
SOT370-1
SOT362-1
相關(guān)PDF資料
PDF描述
VC16241ADGG 16-bit buffer/line driver 3-State
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VC1-1 CAPSULE ANTI CORROSION
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