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參數(shù)資料
| 型號： | VDD8616A8A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Double Data Rate SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 213K |
| 代理商： | VDD8616A8A |
V-Data
VDD8616A8A
AC Characteristics
-75BA
-75B
Parameter
Symbol
Min
Max
Min
Max
Unit
/CAS Latency = 2.5
tCK2.5
7.5
12
7.5
12
System clock
Cycle time
/CAS Latency = 2
tCK2
7.5
12
10
12
ns
Clock high pulse width
tCHW
0.45
0.55
0.45
0.55
CLK
Clock low pulse width
tCLW
0.45
0.55
0.45
0.55
CLK
Access time form CK to /CK
tAC
-0.75
0.75
-0.75
0.75
ns
Data strobe edge to clock edge
tDQSCK
-0.75
0.75
-0.75
0.75
ns
Clock to first rising edge of DQS delay
tDQSS
0.75
1.25
0.75
1.25
CLK
/RAS cycle time
tRC
65
-
65
-
ns
/RAS to /CAS delay
tRCD
20
-
20
-
ns
/RAS active time
tRAS
45
120K
45
120K
ns
/RAS precharge time
tRP
20
-
20
-
ns
/RAS to /RAS bank active delay
tRRD
15
-
15
-
ns
/CAS to /CAS delay
tCCD
1
-
1
-
CLK
Data-in setup time (to DQS)
tDS
0.5
-
0.5
-
ns
Data-in hold time (to DQS)
tDH
0.5
-
0.5
-
ns
DQS Falling Edge to CLK Setup Time
tDSS
0.2
-
0.2
-
CLK
DQS Falling Edge Hold Time from CLK tDSH
0.2
-
0.2
-
CLK
Input setup time
tIS
0.9
-
0.9
-
ns
Input hold time
tIH
0.9
-
0.9
-
ns
DQS-in high level width
tDSH
0.35
-
0.35
-
CLK
DQS-in low level width
tDSL
0.35
-
0.35
-
CLK
Clock to DQS write preamble setup time tWPRES
0
-
0
-
ns
Write preamble
tWPST
0.4
06
0.4
06
CLK
Data strobe edge to output data edge
tDQSQ
0.5
0.5
ns
Mode register set cycle time
tMRD
15
15
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
CLK
Rev 2 April, 2002
7
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| VDD8616A8A-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Double Data Rate SDRAM |
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