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參數(shù)資料
| 型號： | VDLMLB-30.720MHZ |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | XO, clock |
| 英文描述： | VCXO, CLOCK, 30.72 MHz, CMOS/TTL OUTPUT |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, LCC-6 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 100K |
| 代理商： | VDLMLB-30.720MHZ |
V-Type Voltage Controlled Crystal Oscillator
Vectron International 267 Lowell Road, Hudson NH 03051
Tel:1-88-VECTRON-1
e-mail: vectron@vectron.com
Performance Characteristics
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical
Maximum
Units
Frequency
fO
1.024
80.000
MHz
Supply Voltage
1
(+3.3 V)
(+5.0 V)
VDD
2.97
4.5
3.3
5.0
3.63
5.5
V
Supply Current
IDD
12
25
mA
Output Logic Levels
Output Logic High
2
Output Logic Low
2
VOH
VOL
0.9*VDD
0.1VDD
V
Transition Times
Rise Time
2
Fall Time
2
tR
tF
1
3
ns
Tristate
Output Enabled
Output Disabled
VIN
VIL
2.5
0.7
V
Duty Cycle
3
(ordering option)
SYM
40/60 or 45/55
%
Operating temperature (ordering option)
0/70 or –40/85
°C
Test Conditions for APR (+5V option)
VC
0.5
4.5
V
Test Conditions for APR (+3.3V option)
VC
0.3
3.0
V
Absolute Pull Range (ordering option)
APR
±50
±70
±80
±100
ppm
Gain Transfer (See Figure 3)
Positive
ppm/V
Control Voltage Leakage Current
IVCXO
±1
uA
Control Voltage Bandwidth (-3dB)
BW
10
kHz
Phase Noise
10 Hz Offset
100 Hz Offset
1 KHz Offset
10 KHz Offset
100 KHz Offset
1 MHz Offset
-55
-85
-115
-142
-148
-151
dBc/Hz
Package Size
7.49 x 5.08 x 1.8
mm
1. A 0.01uF and a 0.1uF capacitor should be located as close to the supply as possible (to ground) is recommended.
2. Figure 1 defines these parameters. Figure 2 illustrates the equivalent five gate TTL load and operating conditions under which
these parameters are tested and specified.
3. Symmetry is defined as (ON TIME/PERIOD with Vs= 1.4 V for TTL and Vs=2.5 V for CMOS, 5 volt operation, and Vs=1.65V
for 3.3 Volt operation.
Figure 1. Output Waveform
Figure 2. Typical Output Test Conditions (25
±5°C)
80
%
Vs
20
%
t
F
t
R
Period
On Time
+
-
+
-
I
C
V
C
4
3
.1
F
.01
F
15pF
25
6
1
I
DD
650
V
DD
1.8k
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