參數(shù)資料
型號(hào): VESD05A8-HN2
廠商: Vishay Intertechnology,Inc.
英文描述: 8-Lines ESD protection diode array
中文描述: 8線路ESD保護(hù)二極管陣列
文件頁(yè)數(shù): 2/7頁(yè)
文件大?。?/td> 445K
代理商: VESD05A8-HN2
www.vishay.com
2
Document Number 84772
Rev. 1.2, 15-Aug-05
VEMI255A-HS3
Vishay Semiconductors
Max. Output Clamping voltage
at I
PP
= 4 A each Input to Pin 2
Acc. IEC 61000-4-5 measured at
output pin
at I
F
= 4 A each Input to Pin 2
Acc. IEC 61000-4-5
each Input to Pin 2
Acc. IEC 61000-4-5
each Input to Pin 2 at I
R
= 1 mA
each Input to Pin 2; output not
connected;
V
IN
= 0 V ; f = 1 MHz
10 pulses, both polarities Acc. IEC
6100-4-2 device not damaged
Measured in a 50 Ohm system
Measure between input and output;
Pin 2 = not connecte; I
S
= 10 mA
V
C
8
V
Max. Forward Clamping voltage
V
F
4.5
V
Max. Peak pulse current
I
PPM
- 4
4
A
Min. Reverse Breakdown Voltage
V
BR
C
IN
6
V
Input Capacitance
60
pF
ESD-Immunity
V
ESD
±
30 kV
V
Cut-off Frequency
Line Resistance
f
3dB
R
S
100
50
MHz
Parameter
Test Conditions
Synbol
Min.
Typ.
Max.
Unit
Figure 1. 8/20μs Peak Pulse Current wave form
acc. IEC 61000-4-5
Figure 2. Typical small signal transmission (S21) @ Z
0
= 50 Ohm
20
μ
s to 50%
s to 100%
0
10
20
30
40
100 %
8
0 %
60 %
40 %
20 %
0 %
1956
8
I
P
Time in
μ
s
V
I
N
PUT
= 0
V
V
I
N
PUT
= 5
V
Meas
u
red in a 50 Ohm system
1
10
100
1000
10000
0
-5
-10
-15
-20
-25
-30
-35
-40
Fre
qu
ency in MHz
T
19569
Figure 3. Typical Capacitance C
IN
vs. Reverse Voltage V
IN
Figure 4. Typical Input Voltage V
IN
vs. Input Current I
IN
f = 1MHz
0
1
2
3
4
5
70
60
50
40
30
20
10
0
V
I
N
in
V
C
I
N
19570
Filter o
u
tp
u
t not connected
V
I
N
V
I
I
N
in
μ
A
8
7
6
5
4
3
2
1
0
0.01
0.1
1
10
100
1000
10000
10571
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