參數(shù)資料
型號: VFC101KN
英文描述: Synchronized VOLTAGE-TO-FREQUENCY CONVERTER
中文描述: 同步電壓頻率轉換器
文件頁數(shù): 8/10頁
文件大小: 136K
代理商: VFC101KN
8
VFC101
with a one-shot capacitor of 60pF. As with any high-
frequency circuit, careful attention to good power supply
bypassing techniques (see “Power Supplies and Ground-
ing”) is also required.
TEMPERATURE DRIFT
Conventional VFC circuits are affected significantly by
external component temperature drift. Drift of the external
input resistor and timing capacitor required with these de-
vices may easily exceed the specified drift of the VFC itself.
When used with its internal input resistor, the gain drift of
the complete VFC101 circuit is totally determined by the
performance of the VFC101. Gain drift is specified at a full-
scale output frequency of 100kHz. Gain drift remains excel-
lent at higher operating frequency, typically remaining within
specifications at f
FS
= 1MHz.
Drift of the external clock frequency directly affects the
output frequency, but by using a common clock for the VFC
and counting circuitry, this drift can be cancelled.
POWER SUPPLIES AND GROUNDING
Separate analog and digital grounds are provided on the
VFC101 and it is important to separate these grounds to
attain greatest accuracy. Logic sink current flowing in the
f
pin is returned to the digital ground. If this “noisy”
current were allowed to flow in analog ground, errors could
be created. Although analog and digital grounds may even-
tually be connected together at a common point in the
circuitry, separate circuit connections to this common point
can reduce the error voltages created by varying currents
flowing through the ground return impedance. The +5V V
REF
pin is referenced to analog ground.
The power supplies should be well bypassed using capaci-
tors with low impedance at high frequency. A value of 0.1
μ
F
is adequate for most circuit layouts.
The VFC101 is specified for a nominal supply voltage of
±
15V. Supply voltages ranging from
±
7.5V to
±
18V may be
used. Either supply can be up to 28V as long as the total of
both does not exceed 36V. Steps must be taken, however, to
assure that the integrator output does not exceed its linear
range. Although the integrator output is capable of 12V
output swing with 15V power supplies, with 7.5V supplies,
output swing will be limited to approximately 4.5V. In this
case, the comparator input cannot be offset by directly
connecting to the 5V reference output pin. The comparator
input must be connected to a lower voltage point (approxi-
mately 2V.) This allows the integrator output to operate
around a lower voltage point, assuring linear operation. This
threshold voltage does not affect the accuracy or drift of the
VFC as long as it is not noisy. It should not be made too
small, however, or the negative output limitation of the
integrator (–0.2V) may cause saturation. Also, a large inte-
grator capacitor may be used to limit the required integrator
waveform swing to approximately 100mV (see Figure 3.)
FIGURE 5. Circuit Diagram and Integrator Voltage Waveform for Low Power Supply Voltage Operation.
V
TH
+ 100mV
V
TH
– 75mV
V
TH
2.25V
Low Scale (V
Slow Oscilloscope Sweep
120mV)
High Scale (V
Fast Oscilloscope Sweep
8.3V)
Integrator Voltage Waveform (Pin 4)
0.05μF
(2.25V)
Clocked
Logic
Output
One-Shot
+V
CC
f
0 to 50kHz
V
0 to 10V
5V
Reference
C
INT
0.1μF
+V
L
0.1μF
+8V
Clock
100kHz
0.1μF
–V
CC
–V
CC
R
IN
+8V
–8V
2.2k
1.8k
V
TH
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