參數(shù)資料
型號： VG36641641DTL-7
廠商： Electronic Theatre Controls, Inc.
英文描述： CMOS Synchronous Dynamic RAM
中文描述： 同步動態(tài)隨機(jī)存儲器的CMOS
文件頁數(shù)： 27/69頁
文件大?。?/td> 1364K
代理商： VG36641641DTL-7
Document :1G5-0177
Rev.2
Page 27
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
CLK
Command
CAS latency = 2
DQM
Hi - Z
Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
RP
PRE
ACT
DQ
Write
PRE
ACT
t
RP
CAS latency = 3
Hi - Z
D0
D3
D2
D1
D0
D3
D2
D1
DQM
D4
D4
command
DQ
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參數(shù)描述
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