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參數(shù)資料
| 型號(hào)： | VIC64 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | VMEbus Interface Controller(VMEbus 接口控制器) |
| 中文描述： | 總線接口控制器（總線接口控制器） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 249K |
| 代理商： | VIC64 |
VIC64
2
cal resource and the cycle is complete. The VIC64 is capable
of all four VMEbus request levels. In addition, the following
release modes are supported:
Release On Request (ROR)
Release When Done (RWD)
Release On Clear (ROC)
Release Under RMC Control
Bus Capture And Hold (BCAP)
Pin Configurations
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
9
10
11
12
13
14
15
7
8
A02
IPL2*
LIACKO*
LOCATOR
PIN
LIRQ2*
ASIZ1
ICFSEL*
VCC
SLSEL1*
GND
VCC
FCIACK*
LD6
MWB*
Pin Grid Array (PGA)
Bottom View
LIRQ5*
ASIZ0
GND
WORD*
A04
IRQ4*
BLT*
IPL1*
LIRQ1*
LIRQ4*
LIRQ6*
A01
A03
A05
A07
IRQ3*
IRQ7*
IRQ2*
IRQ6*
IRQ1*
A06
GND
SLSEL0*
GND
LIRQ7*
LIRQ3*
IPL0*
LD2
LD5
LD1
LD3
LD0
LD4
LA7
LA3
LA5
LA6
LA2
LA4
LA1
LA0
CS*
DS*
PAS*
IRQ5*
VCC
VCC
VCC
VCC
D00
D01
D04
D03
D05
D06
D07
D02
GND
GND
GND
GND
GND
VCC
GND
LD7
GND
GND
BGOUT0*
BGOUT3*
BGOUT2*
BGIN2*
BGOUT1*
BGIN0*
BGIN3*
BGIN1*
BCLR*
BBSY*
BR1*
BR3*
BR2*
DS1*
DS0*
BR0*
LEDO
LEDI
LADO
LADI
FC2
FC1
SCON*/D64
DDIR
LWDENIN*
DENO*
SIZ0
SIZ1
LBG*
ABEN*
IRESET*
HALT*
DSACK0*
LBR*
RMC*
R/W*
DSACK1*
RESET*
LBERR*
VCC
CLK64M
UWDENIN*
SWDEN*
ISOBE*
SYSCLK
BERR*
WRITE*
AM5
AM3
AM2
AM1
AM0
AM4
AS*
LWORD*
DEDLK*
LAEN
ACFAIL*
IACKOUT*
SYSFAIL*
SYSRESET*
IACKIN*
IACK*
DTACK*
VIC64-1
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