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參數(shù)資料
| 型號： | VJ1206X123KXX |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | N-Channel FET Synchronous Buck Regulator Controller for Low Output Voltages |
| 中文描述： | N溝道場效應(yīng)管同步降壓穩(wěn)壓控制器輸出電壓低 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 602K |
| 代理商： | VJ1206X123KXX |
Block Diagram
20049401
Application Information
THEORY OF OPERATION
The LM2727 is a voltage-mode, high-speed synchronous
buck regulator with a PWM control scheme. It is designed for
use in set-top boxes, thin clients, DSL/Cable modems, and
other applications that require high efficiency buck convert-
ers. It has power good (PWRGD), output shutdown (SD),
over voltage protection (OVP) and under voltage protection
(UVP). The over-voltage and under-voltage signals are OR
gated to drive the Power Good signal and a shutdown latch,
which turns off the high side gate and turns on the low side
gate if pulled low. Current limit is achieved by sensing the
voltage V
DS
across the low side FET. During current limit the
high side gate is turned off and the low side gate turned on.
The soft start capacitor is discharged by a 95μA source
(reducing the maximum duty cycle) until the current is under
control. The LM2737 does not latch off during UVP or OVP,
and uses the HIGH and LOW comparators for the power-
good function only.
START UP
When V
exceeds 4.2V and the enable pin EN sees a logic
high the soft start capacitor begins charging through an
internal fixed 10μA source. During this time the output of the
error amplifier is allowed to rise with the voltage of the soft
start capacitor. This capacitor, Css, determines soft start
time, and can be determined approximately by:
An application for a microprocessor might need a delay of
3ms, in which case C
would be 12nF. For a different
device, a 100ms delay might be more appropriate, in which
case C
would be 400nF. (390 10%) During soft start the
PWRGD flag is forced low and is released when the voltage
reaches a set value. At this point this chip enters normal
operation mode, the Power Good flag is released, and the
OVP and UVP functions begin to monitor Vo.
NORMAL OPERATION
While in normal operation mode, the LM2727/37 regulates
the output voltage by controlling the duty cycle of the high
side and low side FETs. The equation governing output
voltage is:
The PWM frequency is adjustable between 50kHz and
2MHz and is set by an external resistor, R
, between the
FREQ pin and ground. The resistance needed for a desired
frequency is approximately:
L
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