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| 型號： | VL-821-JAW-SAAN-25M0000000 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 25 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-4 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 0K |
| 代理商： | VL-821-JAW-SAAN-25M0000000 |
Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 http://www.vectron.com
Page2
Performance Specifications
Table 1. Electrical Performance, 3.3V Option
Parameter
Symbol
Min
Typical
Maximum
Units
Supply
Operating Supply Voltage1
V
DD
2.97
3.3
3.63
V
Absolute Maximum Operating Voltage
-0.05
5.0
V
Supply Current, Output Enabled
<30 MHz
30.01 to 75 MHz
75.01 to 133 MHz
133.01 to 200 MHz
I
DD
10
15
20
25
mA
Supply Current, Output disable
I
DD
30
uA
Frequency
Frequency
f
O
0.8
200.00
MHz
Stability4, (Ordering Option)
±25, ±50, ±100
ppm
Outputs
Output Logic Levels
Output Logic High2
Output Logic Low2
Output Logic High Drive
Output Logic Low Drive
V
OH
V
OL
I
OH
I
OL
0.9*V
DD
8
0.1*V
DD
V
mA
Output Rise /Fall Time2
t
R
/t
F
5ns
Duty Cycle3
SYM
45
50
55
%
Enable/Disable
Output Enable/Disable5
Output Enable
Output Disable
V
IH
V
IL
0.7*V
DD
0.3V*
DD
V
Internal Enable Pull-Up Resistor
100
Kohm
Start-Up Time
t
SU
10
ms
Operating Temp, (Ordering Option)
T
OP
-10/70 or -40/85
°C
I
DD
V
DD
15pF
4
12
3
.1μF
.01μF
+
t
R
t
F
V
OH
V
OL
50%
On Time
Period
Fig 2: Waveform
Fig 1: Test Circuit
A.0.01 uF and a 0.1uF capacitor should be located as close to the supply as possible (to ground) is recommended. V
1]
DD
supply ramp should be
<100
msec.
Figure 2 defines these parameters. Figure 1 illustrates the operating conditions under which these parameters are tested and specified. For Fo>90MHz,
2]
rise and fall time is measured 20 to 80%.
Symmetry is measured defined as On Time/Period.
3]
Incudes calibration tolerance, operating temperature, supply voltage variations, aging and shock and vibration (not under operation).
4]
Output will be enabled if enable/disable is left open. E/D should be powered up after V
5]
DD
.
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