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參數(shù)資料
| 型號： | VM-702-FHJ-BAAN-460M000000 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 460 MHz, HSCL OUTPUT |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, PLASTIC PACKAGE-6 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 291K |
| 代理商： | VM-702-FHJ-BAAN-460M000000 |
Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 http://www.vectron.com
Environmental and IR Compliance
Table 5. Environmental Compliance
Parameter
Condition
Mechanical Shock
MIL-STD-883 Method 2002
Mechanical Vibration
MIL-STD-883 Method 2007
Temperature Cycle
MIL-STD-883 Method 1010
Solderability
MIL-STD-883 Method 2003
Fine and Gross Leak
MIL-STD-883 Method 1014
Resistance to Solvents
MIL-STD-202 Method 215
Moisture Sensitivity Level
MSL1
Page6
LVPECL Application Diagrams
The VM-702 incorporates a standard LVPECL output scheme, which are un-terminated emitters as shown in Figure 8. There are numerous application
notes on terminating and interfacing LVPECL logic and the two most common methods are a single resistor to ground, Figure 9, and a pull-up/pull-down
scheme as shown in Figure 10. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
Figure 11. Single Resistor Termination Scheme
Figure 12. Pull-Up Pull Down Termination
Resistor values are typically 140 ohms for 3.3V operation
and 82.5ohms for 2.5V operation.
Resistor values are typically for 3.3V operation
For 2.5V operation, the resistor to ground is 62
ohms and the resistor to supply is 250 ohms
100
LVDS
Driver
LVDS
Receiver
100
LVDS
Driver
Receiver
Figure 13. LVDS to LVDS Connection, Internal 100ohm
Figure 14. LVDS to LVDS Connection
External 100ohm and AC blocking caps
Some LVDS structures have an internal 100 ohm resistor on the
input and do not need additional components.
Some input structures may not have an internal 100 ohm
resistor on the input and will need an external 100ohm
resistor for impedance matching. Also, the input may have
an internal DC bias which may not be compatible with
LVDS levels, AC blocking capacitors can be used.
LVDS Application Diagrams
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
140Ω
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