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| 型號(hào)： | VME-64SD1-16MSV1-10 |
| 英文描述： | Converter |
| 中文描述： | 轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 261K |
| 代理商： | VME-64SD1-16MSV1-10 |
Apex Signal, A Division of NAI, Inc.
631.567.1100/631.567.1823(fax)
2-05-01
S 64 SD1 A001 REV A 1.4
170 Wilbur Place, Bohemia, NY, 11716,USA
www.naii.com / e-mail:sales@naii.com
Code:OVGU1
Page 7 of 9
Example
0
1
0
1
0
1
DSP Rev
1.1
FPGA Rev 3
PC Rev
1
Front panel Connectors:
J1: DC37P; Mate: DC37S (not supplied)
J2: DC37P; Mate: DC37S (not supplied)
37 S1
Ch. 1
15 S4
Ch. 2
28 S1
Ch. 4
6 S4
Ch. 5
37 S1
Ch. 7
15 S4
Ch. 8
28 S1
Ch.10
6
S4
Ch.11
36 S3
Ch. 1
32 RHi Ch. 2
27 S3
Ch. 4
23 RHi Ch. 5
36 S3
Ch. 7
32 RHi
Ch. 8
27 S3
Ch.10
23 RHi
Ch.11
19 S2
Ch. 1
14 RLo Ch. 2
10 S2
Ch. 4
5 RLo Ch. 5
19 S2
Ch. 7
14 RLo
Ch. 8
10 S2
Ch.10
5
RLo
Ch.11
18 S4
Ch. 1
31 S1
Ch. 3
9
S4
Ch. 4
22 S1
Ch. 6
18 S4
Ch. 7
31 S1
Ch. 9
9 S4
Ch.10
22 S1
Ch.12
35 RHi Ch. 1
30 S3
Ch. 3
26 RHi Ch. 4
21 S3
Ch. 6
35 RHi Ch. 7
30 S3
Ch. 9
26 RHi
Ch.10
21 S3
Ch.12
17 RLo Ch. 1
13 S2
Ch. 3
8
RLo Ch. 4
4 S2
Ch. 6
17 RLo Ch. 7
13 S2
Ch. 9
8 RLo
Ch.10
4 S2
Ch.12
34 S1
Ch. 2
12 S4
Ch. 3
25 S1
Ch. 5
3 S4
Ch. 6
34 S1
Ch. 8
12 S4
Ch. 9
25 S1
Ch.11
3 S4
Ch.12
33 S3
Ch. 2
29 RHi Ch. 3
24 S3
Ch. 5
20 RHi Ch. 6
33 S3
Ch. 8
29 RHi
Ch. 9
24 S3
Ch.11
20 RHi
Ch.12
16 S2
Ch. 2
11 RLo Ch. 3
7
S2
Ch. 5
2 RLo Ch. 6
16 S2
Ch. 8
11 RLo
Ch. 9
7 S2
Ch.11
2 RLo
Ch.12
1 Chassis
J3: DB25P; Mate: DB25S
Pin
1
S1 Ch.13
14 S4 Ch.13
4
S1 Ch.14
17 S4 Ch.14
7
S1 Ch.15
20 S4 Ch.15
10 S1 Ch.16
23 S4 Ch.16
13 Chassis
2
S3 Ch.13
15 RHi Ch.13
5
S3 Ch.14
18 RHi Ch.14
8
S3 Ch.15
21 RHi Ch.15 11 S3
Ch.16 24 RHi Ch.16
3
S2 Ch.13
16 RLo Ch.13
6
S2 Ch.14
19 RLo Ch.14
9
S2 Ch.15
22 RLoCh.15
12 S2 Ch.16
25 RLo Ch.16
P2 Connector: Uses a 5 row 160 pin connector
Pin
Designation
Pin
Designation
Pin
Designation Pin
Designation
Pin
Designation
Pin
Designation
18c S1
Ch. 1
30a
RLo Ch. 3
21a
RHi
Ch. 6
4c
S4
Ch. 9
11d
S2
Ch. 12
28d S3
Ch. 15
22c S3
Ch. 1
18a
S1
Ch. 4
23a
RLo Ch. 6
1a
RHi Ch. 9
12d
S4
Ch. 12
29d S2
Ch. 15
20c S2
Ch. 1
22a
S3
Ch. 4
11a
S1
Ch. 7
2a
RLo Ch. 9
13d
RHi Ch. 12
30d S4
Ch. 15
24c S4
Ch. 1
20a
S2
Ch. 4
15a
S3
Ch. 7
5c
S1
Ch. 10 14d
RLo Ch. 12
5z
RHi
Ch. 15
29c RHi Ch. 1
24a
S4
Ch. 4
13a
S2
Ch. 7
6c
S3
Ch. 10 15d
S1
Ch. 13
7z
RLo
Ch. 15
27c RLo Ch. 1
27a
RHi Ch. 4
17a
S4
Ch. 7
7c
S2
Ch. 10 16d
S3
Ch. 13
9z
S1
Ch. 16
10c S1
Ch. 2
29a
RLo Ch. 4
8a
RHi
Ch. 7
8c
S4
Ch. 10 17d
S2
Ch. 13
11z S3
Ch. 16
14c S3
Ch. 2
10a
S1
Ch. 5
9a
RLo Ch. 7
3a
RHi Ch. 10 18d
S4
Ch. 13
13z S2
Ch. 16
12c S2
Ch. 2
14a
S3
Ch. 5
11c
S1
Ch. 8
4a
RLo Ch. 10 19d
RHi Ch. 13
15z S4
Ch. 16
16c S4
Ch. 2
12a
S2
Ch. 5
15c
S3
Ch. 8
3d
S1
Ch. 11 20d
RLo Ch. 13
17z RHi
Ch. 16
30c RHi Ch. 2
16a
S4
Ch. 5
13c
S2
Ch. 8
4d
S3
Ch. 11 21d
S1
Ch. 14
19z RLo
Ch. 16
28c RLo Ch. 2
21c
RHi
Ch. 5
17c
S4
Ch. 8
5d
S2
Ch. 11 22d
S3
Ch. 14
19a Int. Ref. Output Hi
25c S1
Ch. 3
23c
RLo Ch. 5
6a
RHi Ch. 8
6d
S4
Ch. 11 23d S2
Ch. 14
19c Int. Ref. Output Lo
32c S3
Ch. 3
25a
S1
Ch. 6
7a
RLo Ch. 8
7d
RHi Ch. 11 24d S4
Ch. 14
26c S2
Ch. 3
32a
S3
Ch. 6
1c
S1
Ch. 9
8d
RLo Ch. 11 25d RHi Ch. 14
31c S4
Ch. 3
26a
S2
Ch. 6
2c
S3
Ch. 9
9d
S1
Ch. 12 26d RLo Ch. 14
28a RHi Ch. 3
31a
S4
Ch. 6
3c
S2
Ch. 9
10d
S3
Ch. 12 27d S1
Ch. 15
S4 pins are used only with Resolvers.
Do not connect to any undesignated pins.
NOTE: P2 is always active
P0 Connector: Only supplied when (A & B) outputs are specified
1e Ch.1 A Hi
4b Ch.3 Index Hi
7a Ch.6 B Hi
10d Ch.9 A Hi
13c Ch.11
Index Hi
17e
Ch.14 B Hi
1d Ch.1 A Lo
4a Ch.3 Index Lo
7b Ch.6 B Lo
10e Ch.9 A Lo
14c Ch.11
Index Lo
17d
Ch.14 B Lo
1a
Ch.1 B Hi
4d Ch.4 A Hi
7c Ch.6 Index Hi
11e Ch.9 B Hi
14b Ch.12 A Hi
17a
Ch.14
Index Hi
1b
Ch.1 B Lo
4e Ch.4 A Lo
8c Ch.6 Index Lo
11d Ch.9 B Lo
14a Ch.12 A Lo
17b
Ch.14
Index Lo
1c Ch.1 Index Hi
5e Ch.4 B Hi
8b Ch.7 A Hi
11a Ch.9 Index Hi
14d Ch.12 B Hi
17c
Ch.15 A Hi
2c Ch.1 Index Lo
5d Ch.4 B Lo
8a Ch.7 A Lo
11b Ch.9 Index Lo
14e Ch.12 B Lo
18c
Ch.15 A Lo
2b
Ch.2 A Hi
5a Ch.4 Index Hi
8d Ch.7 B Hi
11c Ch.10 A Hi
15e Ch.12 Index Hi
18b
Ch.15 B Hi
2a
Ch.2 A Lo
5b Ch.4 Index Lo
8e Ch.7 B Lo
12c Ch.10 A Lo
15d Ch.12 Index Lo
18a
Ch.15 B Lo
2d Ch.2 B Hi
5c Ch.5 A Hi
9e Ch.7 Index Hi
12b Ch.10 B Hi
15a Ch.13 A Hi
18d
Ch.15
Index Hi
2e Ch.2 B Lo
6c Ch5A Lo
9d Ch.7 Index Lo
12a Ch.10 B Lo
15b Ch.13 A Lo
18e
Ch.15
Index Lo
3e Ch.2 Index Hi
6b Ch.5 B Hi
9a Ch.8 A Hi
12d Ch.10 Index Hi
15c Ch.13 B Hi
19e
Ch.16 A Hi
3d Ch.2 Index Lo
6a Ch.5 B Lo
9b Ch.8 A Lo
12e Ch.10 Index Lo
16c Ch.13 B Lo
19d
Ch.16 A Lo
3a
Ch.3 A Hi
6d Ch.5 Index Hi
9c Ch.8 B Hi
13e Ch.11 A Hi
16b Ch.13
Index Hi
19a
Ch.16 B Hi
3b Ch.3 A Lo
6e Ch.5 Index Lo
10c Ch.8 B Lo
13d Ch.11 A Lo
16a Ch.13
Index Lo
19b
Ch.16 B Lo
3c Ch.3 B Hi
7e Ch.6 A Hi
10b Ch.8 Index Hi
13a Ch.11 B Hi
16d Ch.14 A Hi
P2-1z
Ch.16
Index Hi
4c Ch.3 B Lo
7d Ch.6 A Lo
10a Ch.8 Index Lo
13b Ch.11 B Lo
16e Ch.14 A Lo
P2-3z
Ch.16
Index Lo
NOTE: For commutation (A,B,C) outputs: A Hi becomes A, B Hi becomes B, and Index Hi becomes C.
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