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| 型號： | VME-64SD1-16MSV3-11 |
| 英文描述： | Converter |
| 中文描述： | 轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 261K |
| 代理商： | VME-64SD1-16MSV3-11 |
Apex Signal, A Division of NAI, Inc.
631.567.1100/631.567.1823(fax)
2-05-01
S 64 SD1 A001 REV A 1.4
170 Wilbur Place, Bohemia, NY, 11716,USA
www.naii.com / e-mail:sales@naii.com
Code:OVGU1
Page 5 of 9
At Power-ON or System Reset, all parameters are restored to last saved setup and, if POST is enabled, a D3
Test is initiated.
Enter Active Channels: Set the bit corresponding to each channel to be monitored during BIT testing in the
Active Channel Register at 48h. “1”=active; “0”=not used. Omitting this step will produce false alarms, because
unused channels will set faults.
Save Setup: The current setup can be saved by writing 5555h to the Save Register at 4Ah. This location will
automatically clear to 0000h when the save is completed (within 5 seconds). When save is elected, all parameters
are saved. However, any parameter can be changed at will. Saving is optional. If not saved, reenter parameters at
each power up.
To restore factory shipped parameters, write AAAAh to the Save Register at 4Ah, followed by System Reset. Note:
After a SAVE or RESTORE, poll 4Ah and do not perform any other operation until word is at "0".
Read: For single-speed applications (Ratio=1), read individual channels: 1, 2, 3, 4 etc. For two-speed applications,
read only channels (2, 4, 6, 8, etc.) for the combined output. For resolution up to 24-bit, read Hi word, then Lo
word. Hi word, when read, latches Lo word. 24 bit resolution, along with carrier frequency etc., will determine how
many of the 16 channels are available…consult factory for specifics.
Latch: All channels may be latched by writing “1” to D1 of Latch Register at 14h. Reading channel will disengage
latch for that channel.
Ratio: Enter the desired ratio, as a binary number, in the Ratio Register corresponding to the pair of channels to
be used for a two-speed channel. Example: Single speed = 1; 36:1 = 100100.
Two-Speed Lock-Loss: When two Synchros are geared to each other, either electrically or mechanically, in
order to achieve higher accuracy, the misalignment of the Coarse and Fine Synchros must not exceed 90
°/gear ratio
or the digital angle output may not be valid. Should this problem occur, with a given channel pair, the corresponding
bit in the Two-Speed Lock-Loss Register at FAh will be set to “0”.
Velocity Scale Factor: To scale the Max Velocity word for 150 RPS set Velocity Scale Factor = 4095 in HEX
(max velocity word of 7FFFh being max. CW rotation, and 8000h being max. CCW rotation.
Scaling effects only the Velocity output word and not the dynamic performance.
Ex: To get max. velocity word @ 150 rps:
4095(150/150) = 4095 (0FFFh) This is also the Factory setting.
To get max. velocity word @ 50 rps.
4095(150/50) = 12,285 (2FFDh)
To get max. velocity word @ 9.375rps. 4095(150/9.375) = 65,520 (FFF0h) This is also the lowest setting
Velocity Output: Read Velocity Registers of each channel as a 2’s complement word, with 7FFFh being
maximum CW rotation, and 8000h being maximum CCW rotation.
When max. velocity is set to 150 RPS, an actual speed of 10 RPS CW would be read as 0888h.
When max. velocity is set to 150 RPS, an actual speed of 10 RPS CCW would be read as F778h.
When max. velocity is set to 50 RPS, an actual speed of 10 RPS CW would be read as 1999h.
When max. velocity is set to 50 RPS, an actual speed of 10 RPS CCW would be read as E667h.
To convert a velocity word (for example E667h) into RPS: If maximum velocity, set to 50 RPS, then
RPS = 50 x E667h / 32,768 = 50 x -6,553 / 32,768 = -10 RPS
Power-On Self-Test (POST): Will initiate the D3 Test upon power-on, if POST is enabled and saved. Enable by
writing "1" to POST Register at F8h. Disable by writing "0" at F8h and then save setup.
D2 Test Enable: Writing “1” to D2 of Test Register at 0Ch initiates automatic background BIT testing that checks
each channel every 5
° to a test accuracy of 0.05° and monitors each Signal and Reference. An Interrupt (if
enabled) will be set to indicate an accuracy problem or Signal or Reference loss and the results are available in
Status Registers (Signal or Reference loss within 2 sec, accuracy within 45 sec).
A “0” deactivates this test. The
testing is totally transparent to the user, requires no external programming, has no effect on the standard operation
of this card and can be enabled or disabled. Card will (every 30 seconds) write 55h at address 4Ch when D2 is
enabled. User can periodically clear to 0000h and then read 4Ch again, after 30 seconds, to verify that background
BIT testing is activated.
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