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參數(shù)資料
| 型號： | VORTEX86SX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32-BIT x86 Embedded SoC |
| 中文描述： | 32位x86嵌入式系統(tǒng)芯片 |
| 文件頁數(shù)： | 15/30頁 |
| 文件大?。?/td> | 2964K |
| 代理商： | VORTEX86SX |
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Vortex86SX
32-Bit x86 Embedded SoC
Vortex86SX Brief Datasheet
Version 1.001
15
AD24
RI2/PWM1CLK
I
Ring Indicator.
This active low input is for the UART ports. A handshake
signal notifies the UART that the telephone ring signal is detected by the
modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of
the Modem Status Register (MSR). An RI_n signal states the change from low
to high after the last MSR read sets bit 2 of the MSR to a “1”. If bit 3 of the
Interrupt Enable Register is set, the interrupt is generated when RI_n changes
state.
Note:
Bit 6 of the MSR is the complement of RI_n.
PWM Timer1 Clock.
This pin is PWM timer1 external clock input when SB
register C0h bit2 is 1 (PINs for PWM).
Data Terminal Ready.
This is an active low output for the UART port. A
handshake output signal signifies the modem that the UART is ready to
establish data communication link. This signal can be programmed by writing
to bit 0 of Modem Control Register (MCR). The hardware reset will clear the
DTR_n signal to be inactive during the loop-mode operation.
PWM Timer1 Output.
This pin is PWM timer1 output when SB register C0h
bit2 is 1 (PINs for PWM).
COM2 TX Status.
This pin will be high when COM2 is trnamitting.
PWM Timer2 Gate.
This pin is PWM timer2 gate mask when SB register C0h
bit2 is 1 (PINs for PWM).
AC25
DTR2/PWM2OUT
O
AE25
TXD_EN2/PWM2GATE
I/O
z
COM3, 4, 9 (6 PIN)
PIN No.
Symbol
Type
Description
G3
SIN3
I
COM3 Receive Data.
FIFO UART receiver serial data input signal.
COM3 Transmit Data.
FIFO UART transmitter serial data output from the
serial port.
COM4 Receive Data.
FIFO UART receiver serial data input signal.
COM4 Transmit Data.
FIFO UART transmitter serial data output from the
serial port.
COM9 Receive Data.
FIFO UART receiver serial data input signal.
COM9 Transmit Data.
FIFO UART transmitter serial data output from the
serial port.
G2
SOUT3
O
N6
SIN4
I
M6
SOUT4
O
K6
SIN9
I
J6
SOUT9
O
z
IDE 0, 1/COM3,4,PRINT1 Interface (58 PINs)
PIN No.
Symbol
Type
Description
K4, K5, L5,
M4, K3, M2,
L2, K2
PD[7:0]/SDD[7:0]
I/O
Parallel port data bus bit .
Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
IDE Secondary Channel Data Bus.
SLCT.
An active high input on this pin indicates that the printer is selected.
Refer to the description of the parallel port for definition of this pin in ECP and
EPP mode.
IDE Secondary Channel Data Bus.
PE.
An active high input on this pin indicates that the printer has detected the
end of the paper. Refer to the description of the parallel port for the definition
of this pin in ECP and EPP mode.
IDE Secondary Channel Data Bus.
BUSY.
An active high input indicates that the printer is not ready to receive
data. Refer to the description of the parallel port for definition of this pin in
ECP and EPP mode.
IDE Secondary Channel Data Bus.
N5
SLCT/SDD8
I/O
L6
PE/SDD9
I/O
M5
BUSY/SDD10
I/O
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