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參數(shù)資料
| 型號： | VP101-3BADP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | DAC |
| 英文描述： | 30/50MHz 8-BIT CMOS VIDEO DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.015 us SETTLING TIME, 8-BIT DAC, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 294K |
| 代理商： | VP101-3BADP |
VP101
7
PCB LAYOUT CONSIDERATIONS
To obtain the optimum performance from the VP101
great care must be taken in the PCB layout to ensure low
noise power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Power and Ground Planes
The VP101 and its associated circuitry should have its
own power/ground planes connected at a single point
through a ferrite bead. It is important that the regular PCB
and ground planes do not overlay any portions of the analog
power or ground planes to minimise plane-to-plane noise
coupling.
Digital Signal Interconnect
The digital signal lines to the VP101 should be isolated
as much as possible from the analog circuitry. Due to the
high clock rates used, the clock lines to the VP101 should be
as short as possible to minimise noise pickup.
Any pull-up resistors used on the inputs should be
connected to the regular PCB power plane, not to the analog
power plane.
Supply Decoupling
Noise on the analog power plane will be further reduced
by the use of multiple decoupling capacitors (See Fig. 5).
Optimum performance is obtained with 0.1
μ
F chip
ceramic capacitors placed as close as possible to the V
AA
pins, with the shortest leads possible to reduce lead
inductance.
It should be noted that while the loop amplifier circuitry
of the VP101 will reject power supply noise, this rejection
decreases with frequency. Any high frequency noise on the
regular supply (such as produced by a switch mode power
supplies) must be adequately suppressed, else the designer
should consider using a three terminal regulator to supply
the analog power plane.
Analog Signal Interconnect
For optimum performance the analog output connectors
and source termination resistors should be as close as
possible to the VP101 to minimise noise pickup and
reflections due to impedance mismatch. The video out
signals should overlay the ground plane and not the analog
power plane, to maximise the high frequency power supply
rejection.
Fig.5 VP101 typical connections
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VP101-3BAGP | 30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-3BAHP | 30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BADP | 30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BAHP | 30/50MHz 8-BIT CMOS VIDEO DAC |
| VP1040 | LOW-POWER CAN TRANSCEIVER WITH BUS WAKE-UP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP101-3BAGP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-3BAHP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BADP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BAHP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5MAHP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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