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參數(shù)資料
| 型號： | VP101-3BAGP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | DAC |
| 英文描述： | 30/50MHz 8-BIT CMOS VIDEO DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.015 us SETTLING TIME, 8-BIT DAC, PQFP44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 294K |
| 代理商： | VP101-3BAGP |
VP101
4
NOTE: Typical with full scale IOG = 26.68mA, R
SET
= 542
, V
REF
= 1.2V, I
SYNC
connected to IOG
Table 1: Video output truth table
Full Scale output current is set by an external resistor
(R
SET
) between the FS ADJUST pin and AGND. R
SET
has a
typical value of 542
for generation of RS-343A video into a
37.5
load. The VP101 may be used in applications where
an external 1.2V (typical) reference is provided, in which
case the external reference should be temperature
compensated and provide a low impedance output.
The D-A converters on the VP101 use a segmented
architecture in which bit currents are routed to either the
output or AGND by a sophisticated decoding scheme.This
architecture eliminates the need for precision component
ratios and greatly reduces the switching transients
associated with turning current sources on or off.
Monotonicity and low glitch energy are guaranteed by using
identical current sources and current steering their outputs.
An on-chip operational amplifier stabilises the full scale
output current against temperature and power supply
variations.
The analog outputs of the VP101 are capable of directly
driving a 37.5
load, such as a doubly terminated 75
co-
axial cable or interpolation filters.
CIRCUIT DESCRIPTION
As shown in the Fig. 2, the VP101 contains three 8-bit
D-A converters, input latches, and a loop amplifier.
On the rising edge of each clock cycle, (see Fig. 4), 24
bits of colour information (R
0
-R
7
, G
0
-G
7
, and B
0
-B
7
) are
latched into the device and presented to the three 8-bit D-A
converters. The REF WHITE input, also latched on the rising
edge of each clock cycle, and will force the inputs of each D-
A converter to $FF.
SYNC and BLANK are latched on the rising edge of the
clock to maintain synchronisation with the colour data. These
inputs add appropriately weighted currents to the analog
outputs, producing the specific output levels required for
video applications as shown in Fig. 3. Table 1 details how the
SYNC, BLANK, and REFWHITE inputs modify the output
levels.
The I
SYNC
current output is typically connected directly
to the IOG output and is used to encode sync information
onto the IOG output. If I
SYNC
is not connected to the IOG
output, sync information will not be encoded on the green
channel, and the IOR, IOG and IOB outputs will have the
same full scale output current.
Fig.3 Composite video output waveform
Description
IOG
(mA)
IOR/IOB
(mA)
REF
WHITE
SYNC
BLANK
DAC
I/P Data
White Level
26.68
19.06
1
1
1
$XX
White Level
26.68
19.06
0
1
1
$FF
Data
Data + 9.06
Data + 1.44
0
1
1
Data
Data-Sync
Data + 1.44
Data + 1.44
0
0
1
Data
Blank Level
9.06
1.44
0
1
1
$00
Blank-Sync
1.44
1.44
0
0
1
$00
Blank Level
7.62
0
X
1
0
$XX
Sync Level
0
0
X
0
0
$XX
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP101-3BAHP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BADP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BAHP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5MAHP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| VP1-0190 | 制造商:COOPER BUSSMANN 功能描述:Ind Power Wirewound 12.2uH 20% Ferrite 850mA T/R |
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