參數(shù)資料
型號: VP101-3BAHP
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: DAC
英文描述: 30/50MHz 8-BIT CMOS VIDEO DAC
中文描述: PARALLEL, 8 BITS INPUT LOADING, 0.015 us SETTLING TIME, 8-BIT DAC, PQCC44
封裝: HP44
文件頁數(shù): 6/10頁
文件大?。?/td> 294K
代理商: VP101-3BAHP
VP101
5
Pin name
Description
BLANK
Composite blank control input. A logic ‘0’ forces the IOR, IOG and IOB outputs to the blanking level, as
illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK is a logic zero, the R
0
-R
7
, G
0
-
G
7
, B
0
-B
7
, and REF WHITE inputs are ignored.
SYNC
Composite sync control input. A logic ‘0’ on this input switches off a 40 IRE current source on the I
SYNC
output. SYNC does not override any other control or data input as shown in Table 1; therefore it should be
asserted only during the blanking interval. It is latched to the rising edge of CLOCK.
REF
WHITE
Reference white level control input. A logic ‘1’ on this input forces the IOR, IOG and IOB outputs to the white
level, regardless of the R
0
-R
7
, G
0
-G
7
and B
0
-B
7
inputs. It is latched on the rising edge of CLOCK. See table 1.
R
0
-R
7
G
0
-G
7
B
0
-B
7
Red, Green, and Blue data inputs. R
0
, G
0
, and B
0
are the least significant data bits. They are latched on the
rising edge of CLOCK. Coding is binary. Unused inputs should be connected to either the regular PCB power
or ground plane.
CLOCK
Clock input. The rising edge of CLOCK latches the R
0
-R
7
, G
0
-G
7
and B
0
-B
7
SYNC, BLANK, and REFWHITE
inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be
driven by a dedicated CMOS buffer.
IOR,IOG,
IOB
Red, Green, and Blue current outputs. these high impedance current sources are capable of directly driving a
doubly terminated 75
co-axial cable. All outputs, whether used or not, should have the same output load
(Note: A DC path to ground must be maintained).
I
SYNC
Sync current output. Typically this current output is directly wired to the IOG output, and enables sync
information to be encoded onto the green channel. A logic ‘0’ on the SYNC input results in no current being
output to this pin, while logic ‘1’ results in the following current being output:
I
SYNC
(mA) = 3468 X
111 LSBs
If sync information is not required on the green channel, this output may be connected to V
AA
and the SYNC
input tied high, causing the I
SYNC
current source to be turned off, reducing the power consumption.
FS
ADJUST
Full scale adjust control. A resistor (R
SET
) connected between this pin and AGND controls the magnitude of
the full video signal (Fig. 3). The current flowing in the R
SET
resistor is equal to 32 LSBs. note that the IRE
relationships in Fig. 3 are maintained, regardless of the full scale output current.
The relationship between R
SET
and full scale current on IOG (assuming I
SYNC
is connected to IOG) is:
V
IOG (mA) = 12082 X
387 LSBs
The full scale output current on IOR, IOB (mA) for a given R
SET
is defined as:
IOR, IOB (mA) = 8624 X
276 LSBs
COMP
Compensation pin. This pin provides compensation for the internal loop amplifier. A 0.01
μ
F ceramic capacitor must
be connected between this pin and the nearest V
AA
pin.
Connecting the capacitor to V
AA
rather than to the AGND provides the highest possible power supply noise
rejection.
V
REF
Voltage reference output. The output from an internal reference circuit, providing 1.2V (typical) reference.A
0.1
μ
F ceramic capacitor must be used to decouple this output to V
AA
.
AGND
Analog ground. All AGND pins must be connected.
V
AA
Analog power. All V
AA
pins must be connected.
V
(V)
SET
(
)
R
SET
(
)
V
(V)
R
SET
(
)
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