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參數(shù)資料
| 型號(hào)： | VP1058FCGDPAS |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 8-BIT, 25MHz, VIDEO FLASH ADC (SINGLE + 5V SUPPLY) |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP28 |
| 封裝： | PLASTIC, DP-28 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 430K |
| 代理商： | VP1058FCGDPAS |
VP1058
GENERAL CIRCUIT DESCRIPTION
The VP1058 employs a 'flash' architecture consisting of a
reference resistor chain, an array of 256 comparators,
encoding logic, and a full 8-bit D-type output latch. The 255
reference levels generated by the resistor chain are compared
with the analog input signal by the comparator array. This
produces a thermometer code which the encoding logic
coverts into an 8-bit word. The D-type latch accepts this data
and holds the outputs until the next conversion. The format of
the output data is determined by the NLINV and NMINV
control lines.
Analog Input
The maximum amplitude and offset of the input is defined
by the setting of the two reference voltages V
and V
. A
signal outside this range will cause the output to be either full-
scale positive or full-scale negative, depending on whether the
signal is off scale in the positive or negative direction.
For optimum performance, the input signal should be
biased at +4.0V with a 2V peak-to-peak amplitude. The
necessary gain, offset and low impedance drive required for
the input signal can be provided by use of a high slew rate ADC
driver.
Reference Voltage
The reference chain between pins V
and V
is formed of
256 series resistors and has a total resistance of
approximately 90
. A mid-reference pin, V
, is provided for
precise setting of the integral linearity, although adjustment is
not necessary to meet the data sheet specification.
The VP1058 will convert analog signals in the range V
<
A
< V
, where V
and V
are in the range +3V to +5V. (The
design of the VP1058 has been optimised for VRB = 3V and
VRT = 5V). All reference pins should be adequately
decoupled close to the device.
Output Format
The output data format is controlled by the logic levels at
the NLINV and NMINV pins as shown on the output coding
table. These inputs are active low and may be tied to DV
for
logic '1' or DGND for logic '0'. Both inputs are considered DC
controls and as such should only be altered while the
converter is in the steady state.
True
NMINV = 1
NLINV = 1
0000 0000
0000 0001
G
0111 1111
1000 0000
1000 0001
G
1111 1110
1111 1111
Table 1 Output coding
Inverted
0
0
1111 1111
1111 1110
G
1000 0000
0111 1111
0111 1110
G
0000 0001
0000 0000
True
0
1
1000 0000
1000 0001
G
1111 1111
0000 0000
0000 0001
G
0111 1110
0111 1111
Inverted
1
0
0111 1111
0111 1110
G
0000 0000
1111 1111
1111 1110
G
1000 0001
1000 0000
20.V Full Scale
7.8431mV Step
5.0V
4.9922V
G
4.0039V
3.9961V
3.9882V
G
3.0079V
3.0V
2.048V Full Scale
8.0mV Step
5.0V
4.9922V
G
3.9840V
3.9760V
3.9680V
G
2.9680V
2.960V
000
001
G
127
128
129
G
254
255
Offset 2s' complement
Binary
Input voltage
Code
40μA
40μA
AGND
AV
CC
A
IN
V
RB
V
RT
Fig.4 Analog input
Fig.5 TTL output stage
DV
CC
DGND
OUTPUT
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