參數(shù)資料
型號(hào): VP7610CGFPIR
廠商: Electronic Theatre Controls, Inc.
英文描述: COLOUR DIGITAL VIDEO CAMERA DECODER IC
中文描述: 彩色數(shù)字?jǐn)z像機(jī)解碼器IC
文件頁(yè)數(shù): 7/14頁(yè)
文件大小: 248K
代理商: VP7610CGFPIR
6
VP7610
53
In
TST1
Test Pin - This pin should be tied low.
61
In
TST2
Test Pin - This pin should be tied low.
62
In
TST3
Test Pin - This pin should be tied low.
63
In
TST4
Test Pin - This pin should be tied low.
71
In
TSTOE
Test Output Enable - This pin should be tied high.
Out
TOUT
Test Outputs - These pins should be unconnected.
In
GND
Power
In
VDD
Power
64, 65, 66,
67, 70, 72,
73, 74, 77,
78, 79, 80,
81, 92, 93,
94, 95, 96,
97, 98, 99
1, 7, 19,
25, 32, 51,
57, 69, 75,
82,
8, 18, 26,
33, 50, 58,
68, 76, 83,
100
REGISTER DESCRIPTIONS
The VP7610 iCamHost processor station address is strap-configurable to any even location between 0x60 and 0x6E
inclusive. Since most iCam cameras currently built use the Station Address 0x68, it is recommended that the iCamHost be
strapped to a different address. The register addresses shown below are the sub-addresses written to the iCamHost
immediately after the Station Address. The 7 LSBs of the sub-address must match the specified address. The MSB of the
sub-address controls the auto-increment feature of the iCamHost. If the MSB of the sub-address is a ‘1’, (sub-addresses
0x80 through 0xFF), the sub-address register in the iCamHost is incremented to the next address immediately after the data
register is read or written. If the MSB of the sub-address is a ‘0’, (sub-addresses 0x00 through 0x7F), the sub-address register
in the iCamHost remains constant regardless of any reads or writes to the data register.
Address 0x00 Configuration Control Register
Read/Write
Bits 7 - 4
Always read as ‘0’
Bit 3
Cfg3 - Camera Input Port Enable
‘1’ CamPort ‘B’ is source
‘0’ CamPort ‘A’ is source
Bit 2
Cfg2 - Colour Bar Enable
‘1’ Colour Bar Test Pattern Output
‘0’ Normal Video Output
Bit 1
Cfg1 - RGB to YUV Converter Bypass
‘1’ Green + BnR Pattern Output
‘0’ Normal YUV Output
Bit 0
Cfg0 - Separator Bypass
‘1’ Sum = CCD Data, Diff = 0
‘0’ Normal Separator Output
7
0
6
0
5
0
4
0
3
Cfg3
2
Cfg2
1
Cfg1
0
Cfg0
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