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參數(shù)資料
| 型號(hào)： | VRC4171A |
| 廠商： | NEC Corp. |
| 英文描述： | Companion Chip for VR4100 Family MIPS RISC Microprocessor(VR4100系列RSIC微處理器的配對(duì)芯片) |
| 中文描述： | 同伴芯片為VR4100家庭的MIPS RISC微處理器（VR4100系列重結(jié)晶微處理器的配對(duì)芯片） |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大小： | 114K |
| 代理商： | VRC4171A |
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10
V
RC
4171A Companion Chip
Note:
MCLK is from either XTAL on X1 and X2 or from the external oscillator.
Table 7. DRAM Read Cycle Characteristics
(refer to Figure 4)
Description
Symbol
Min.
Max.
Unit
Row address setup time
t
ASR
T
ns
Row address hold time
t
RAH
T–5
ns
Column address setup
t
ASC
T
ns
Column address hold time
t
CAH
T
ns
*VRAS pulse width
t
RAS
4.5T
ns
*VRAS precharge time
t
RP
3.5 T–3
ns
*VRAS to *VCAS delay time
t
RCD
3.5 T + 2
ns
*VCAS hold time
t
CSH
3 T + 2
ns
*VCAS pulse width
t
CAS
T – 1
ns
*VCAS precharge time
t
CP
T
ns
Data access time from *VRAS
t
RAC
4.5 T + 3
ns
Data access time from *VCAS
t
CAC
T + 3
ns
Table 8. DRAM Write Cycle Characteristics
(refer to Figure 5)
Description
Symbol
Min.
Max.
Unit
Row address setup time
t
ASR
T
ns
Row address hold time
t
RAH
T–5
ns
Column address setup
t
ASC
T
ns
Column address hold time
t
CAH
T
ns
*VRAS pulse width
t
RAS
4.5 T
ns
*VRAS precharge time
t
RP
3.5 T–3
ns
*VCAS to *VRAS precharge time
t
CRP
3 T
ns
*VCAS hold time
t
CSH
3 T+2
ns
*VCAS pulse width
t
CAS
T– 1
ns
*VCAS precharge time
t
CP
T
ns
*VRAS to *VCAS delay time
t
RCD
3.5 T+2
ns
Write pulse setup time from *VCAS
t
WCS
2T
ns
Write pulse hold time from *VCAS
t
WCH
T
ns
Data setup time to *VCAS
t
DS
8
ns
Data hold time to *VCAS
t
DH
12
ns
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