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參數(shù)資料
| 型號： | VRC5074 |
| 廠商： | NEC Corp. |
| 英文描述： | Interface Controller(接口控制器) |
| 中文描述： | 接口控制器（接口控制器） |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 27K |
| 代理商： | VRC5074 |
2
V
RC
5074
PCI Interface
Full compliance with PCI Local Bus Specification (rev. 2.1)
Four possible configurations
— 66-MHz, 64-bit bus (maximum sustained bandwidth of 533 Mbps)
— 66-MHz, 32-bit bus (maximum sustained bandwidth of 267 Mbps)
— 33-MHz, 64-bit bus (maximum sustained bandwidth of 267 Mbps)
— 33-MHz, 32-bit bus (maximum sustained bandwidth of 133 Mbps)
3.3-volt compliant; 5-volt tolerant
Initiator capability for CPU, DMA, and local bus master
Two programmable address windows
Target capability for access to all V
Eleven programmable address windows controlled by BARs (base address registers)
Four simultaneous delayed read cycle transactions
32-deep, 8-byte-wide output FIFOs with address/data from V
32-deep, 8-byte-wide input FIFO with address/data from PCI to V
Full target and initiator burst support
Burst lengths of up to 2 MB for both read and write cycles
Optional PCI central resource services
— Arbitration for five other PCI devices
— Four PCI interrupt lines plus one sideband interrupt
PCI clock buffered to five other PCI devices
PCI clock derived from CPU clock or external source
64-bit addressing with dual address cycle (target and initiator)
Semaphore operation (locked cycles) as target and initiator
Full configuration space for standalone operation
RC
5074 resources
RC
5074 initiator to PCI
5074 resources
RC
Local I/O Interface
Seven flexibly programmable device chip selects and one boot ROM chip select
Very flexible bus control signal relationships and durations
Fixed internal timing or optional external ready/acknowledge signal
External local bus masters support
Chip select support for up to 4 GB of address space
Local I/O available only if 32-bit PCI bus is used
3.3-volt outputs; 5-volt tolerant inputs
DMA Controller
Block transfers from/to any physical address and from/to any bank
32 D-word (256-byte) buffer
Two sets of control registers for chained operation
All combinations of unaligned transfers supported
Transfers at maximum PCI bandwidth
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