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參數資料
| 型號： | VS1664648041BTGA-8L |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 64 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數： | 14/15頁 |
| 文件大?。?/td> | 188K |
| 代理商： | VS1664648041BTGA-8L |
Document:1G5-0115
Rev.4
Page 8
VIS
VS864648041B,VS1664648041B
Preliminary
8M,16MX64-Bit
SDRAM Module
DC Characteristics(Recommended Operating Conditions unless otherwise noted)
Notes 1. ICC depends on output loading and cycle rates. Specified values are obtained with the output open.
2. ICC is measured on condition that addresses are changed only one time during tCK(MIN.).
Parameter
Symbol
Test Conditions
VS1664648041B
-8H
-8L
10
Unit Notes
Min
Max
Min Max Min Max
Operating current
ICC1
Burst length = 1One
bank active, Io = 0mA
(MIN)
CL = 3
840
740
mA
1,2
CL = 2
800
700
Precharge standby
current in power
down mode
ICC2P
IL(MAX), tCK = 10ns
48
mA
ICC2PS
IL(MAX), tCK =
32
Precharge standby
current in Nonpower
down mode
ICC2N
IH(MIN), tCK = 10ns
IH(MIN)
Input signals are changed
one time during 2 clk cycles
400
mA
ICC2NS
IH(MIN), tCK =
IL(MAX)
Input signals are stable
120
Active standby current
in power down mode
ICC3P
IL(MAX) ,tCK = 10ns
90
mA
ICC3PS
IL(MAX), tCK =
80
Active standby current
in nonpower down
mode
ICC3N
IL(MAX), tCK = 10ns
IL(MIN)
Input signals are changed
one time during 2 clk cycles
400
mA
ICC3NS
IH(MIN), tCK =
IL(MAX)
Input signals are stable
200
Operating current
(Burst mode)
ICC4
(MIN),Io = 0mA
Burst length=4
CL = 3
1160
930
mA
1,2
CL = 2
820
680
550
Refresh current
ICC5
(MIN)
2200
1920 mA
2
Self refresh current
ICC6
32
mA
Input leakage current
(Inputs)
ILI
(MAX)
Pins not under test = 0V
-80
80
-80
80
-80
80
uA
Output leakage current
(I/O pins)
ILO
(MAX)
DQ# in H - Z., Dout disabled
-10
10
-10
10
-10
10
uA
Output Low Voltage
VOL
IOL = 2mA
0.4
V
Output High Voltage
VOH
IOH = -2mA
2.4
V
t
R C
t
RC
≥
CKE
V
≤
CKE
V
≤
∞
CKE
V
≥
CS
V
≥
CKE
V
≥
∞
CLK
V
≤
CKE
V
≤
CKE
V
≤
∞
CKE
V
≥
CS
V
≥
CKE
V
≥
∞
CLE
V
≤
t
C K
t
C K
≥
t
R C
t
RC
≥
CKE
0.2V
≤
0
V
I N
<
V
D D
≤
0
V
OUT
<
V
DD
≤
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