參數(shù)資料
型號(hào): VS6552V02C
廠商: 意法半導(dǎo)體
英文描述: VGA Color CMOS Image Sensor Module
中文描述: VGA彩色CMOS圖像傳感器模塊
文件頁(yè)數(shù): 6/26頁(yè)
文件大?。?/td> 800K
代理商: VS6552V02C
VS6552
6/26
3 FUNCTIONAL DESCRIPTION
The first sections of this chapter detail the main
blocks in the device:
Analog video block
Digital video block
The later sections of this chapter describe other
functional aspects of the device. Device level op-
erating modes, including suspend, are detailed
3.1 Analog Video Block
3.1.1 Features
ADC: 10-bit A/D converter - SRAM readout
Dynamic range 60 dB (typical)
SNR 37 dB @ 50 cd.m
2
(typical)
Figure 2. Analog Video Block
3.1.2 Analogue Block Diagram
The analog video block from
Figure 4
, consists of
a VGA resolution pixel array, power management
circuitry. The digital block provides all timing sig-
nals to drive the analog block.
Pixel voltage values are read out and digitized us-
ing the address decoders and column ADC
3.2 Digital Video Block
3.2.1 Features
Frame rate: 30 frame/s max. (VGA) can be
reduced down to less than 3 frame/s (VGA)
Automatic dark calibration to ensure consistent
video level over varying scenes
Fixed pattern noise (FPN) data gathering
Line and frame statistics gathering
On-chip Power-On-Reset cell
Single video output format: VGA 640 x 480
H - Scaler function to aid software only
viewfinder implementations
3.2.2 Dark Calibration Algorithm
VS6552 runs a dark calibration algorithm on the
raw image data to control the video offsets caused
by dark current. This ensures that a high quality
image is output over a range of operating condi-
tions. First frame dark level is correctly calibrated,
for subsequent frames the adjustment of the dark
level is damped by a leaky integrator function to
avoid possible frame to frame flicker.
VGA
pixel
array
Y address
Digital
logic
raw sensor data
Timing signals
Timing signals
Power
management
Column ADC
X-Address
SRAM readout
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