參數(shù)資料
型號: VS864648041BTGA-8H
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 8M X 64 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 2/15頁
文件大?。?/td> 188K
代理商: VS864648041BTGA-8H
Document:1G5-0115
Rev.4
Page 10
VIS
VS864648041B,VS1664648041B
Preliminary
8M,16MX64-Bit
SDRAM Module
Serial presence detect information
VS864648041B (64MB version)
Byte
Function described
Function Supported
HEX
-8H
-8L
10
-8H
-8L
10
0
Number of bytes used by Vanguard
128bytes
80
1
Total SPD memory size
256bytes
08
2
Memory type
SDRAM
04
3
Number of row addresses
12
0C
4
Number of column addresses
9
09
5
Number of banks on module
1row
01
6
Module data width
64bits
40
7
Module data width (continued)
0
00
8
Module voltage interface lelevls
LVTTL
01
9
SDRAM cycle time. CAS latency =3
10ns
A0
10
SDRAM access from clock. CAS latency =3
6ns
60
11
Module configuration type
Non - Parity
00
12
Refresh rate/type
15.6us/self
80
13
SDRAM width, primary SDRAM
x8
08
14
Error checking SDRAM data width
N/A
00
15
Min. clock delay, back to
back random column address
1
01
16
Burst length supported
1,2,4,8 & Page
8F
17
Number of banks on each SDRAM device
4
04
18
CAS latencies supported
2 & 3
06
19
CS latency
0 CLK
01
20
Write latency
0 CLK
01
21
SDRAM module attributes
Non-buffered
00
22
SDRAM device attributes: general
0E
23
SDRAM cycle time. CAS latency =2
10ns
12ns
15ns
A0
C0
E0
24
SDRAM access from clock. CAS latency =2
6ns
60
27
Min. row precharge time
20ns
30ns
14
1E
28
Min. row active to row active
20ns
14
29
Min. RAS to CAS delay
20ns
30ns
14
1E
30
Min. RAS pulse width
50ns
60ns
2E
32
31
Module bank density
64MB
10
32
Command and address input setup time
2ns
3ns
20
30
33
Command and address input hold time
1ns
10
34
Data input setup time
2ns
3ns
20
30
35
Data input hold time
1ns
10
62
SPD data revision code
Rev.1.2
12
63
Checksum for bytes 0-62
Checksum data
01
21
79
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