
Trademarks
TM
Vitesse, ASIC-Friendly, FibreTimer, TimeStream, Snoop Loop, Super FEC, FOCUSConnect, Meigs-II, Meigs-IIe, Lansing, Campbell-I, Barrington,
PaceMaker, HOVCAT48, HOVCAT48e, HOVCAT192, HOVCAT192e, Micro PHY, FOCUS32, FOCUS16, IQ2200, NexSAS, VersaCAT, GigaStream, HawX,
SparX, StaX, VstaX, SimpliPHY,VeriPHY, ActiPHY, XFP PRO, SFP PRO, Smart-LINK, OctalMAC, EQ Technology are trademarks in the United States and/or
other jurisdictions of Vitesse Semiconductor Corporation. All other trademarks or registered trademarks mentioned herein are the property of their respective
holders.
Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications to improve performance, reliability or
manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is
subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by
Vitesse for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent
right of any manufacturer.
Copyright 2006
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VSC3144
Line Cards
FPGA/
ASIC
OE
BACK PL ANE APPL ICATION:
B
a
c
k
p
l
a
n
e
VSC3144
Central Switch
GE NE R AL DE S CR IPTION:
S PE CIF ICATIONS :
programmed to connect to any of its inputs. The
signal path through the device uses no registers and
is fully asynchronous. This means there are no restrictions on the phase,
frequency, or signal pattern of any input.
A high degree of signal integrity is maintained throughout the VSC3144
device because each high-speed output is a fully differential,
switched-current driver with on-die termnations. Data inputs are
termnated on-die using 100 resistors between true and complement
inputs, with a common connection to an internal bias source, which
facilitates AC coupling to the switch inputs.
Core programmng for the VSC3144 device can be sequential on a
port-by-port basis, or multiple programassignments can be queued and
issued simultaneously using the CONFIG bit. The entire device can be
initialized for straight-through, multicast, or other configurations. Unused
channels can be powered down to allow efficient use of the switch in
applications that require only a subset of the available I/O channels.
Power-down is enabled in the software by programmng individual unused
outputs with a power-down code.
`
6.5 Gbps NRZ per-channel data rate
`
2.5 V power supply (2.5 V or 3.3 V programport power supply)
`
2.5 V or 3.3 V CMOS TTL-compatible I/O
`
Differential CML I/O with integrated termnation impedance
`
0
°C to 85
°C operating temperature range